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f2a8bd2e92
Register the wireleass mac clock on rt2880. This is required by the wifi driver. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/8006/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
145 lines
3.4 KiB
C
145 lines
3.4 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Parts of this file are based on Ralink's 2.6.21 BSP
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*
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* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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* Copyright (C) 2013 John Crispin <blogic@openwrt.org>
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <asm/mipsregs.h>
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#include <asm/mach-ralink/ralink_regs.h>
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#include <asm/mach-ralink/rt288x.h>
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#include "common.h"
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static struct ralink_pinmux_grp mode_mux[] = {
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{
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.name = "i2c",
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.mask = RT2880_GPIO_MODE_I2C,
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.gpio_first = 1,
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.gpio_last = 2,
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}, {
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.name = "spi",
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.mask = RT2880_GPIO_MODE_SPI,
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.gpio_first = 3,
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.gpio_last = 6,
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}, {
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.name = "uartlite",
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.mask = RT2880_GPIO_MODE_UART0,
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.gpio_first = 7,
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.gpio_last = 14,
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}, {
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.name = "jtag",
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.mask = RT2880_GPIO_MODE_JTAG,
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.gpio_first = 17,
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.gpio_last = 21,
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}, {
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.name = "mdio",
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.mask = RT2880_GPIO_MODE_MDIO,
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.gpio_first = 22,
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.gpio_last = 23,
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}, {
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.name = "sdram",
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.mask = RT2880_GPIO_MODE_SDRAM,
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.gpio_first = 24,
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.gpio_last = 39,
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}, {
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.name = "pci",
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.mask = RT2880_GPIO_MODE_PCI,
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.gpio_first = 40,
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.gpio_last = 71,
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}, {0}
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};
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static void rt288x_wdt_reset(void)
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{
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u32 t;
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/* enable WDT reset output on pin SRAM_CS_N */
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t = rt_sysc_r32(SYSC_REG_CLKCFG);
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t |= CLKCFG_SRAM_CS_N_WDT;
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rt_sysc_w32(t, SYSC_REG_CLKCFG);
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}
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struct ralink_pinmux rt_gpio_pinmux = {
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.mode = mode_mux,
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.wdt_reset = rt288x_wdt_reset,
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};
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void __init ralink_clk_init(void)
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{
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unsigned long cpu_rate, wmac_rate = 40000000;
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u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
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t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
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switch (t) {
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case SYSTEM_CONFIG_CPUCLK_250:
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cpu_rate = 250000000;
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break;
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case SYSTEM_CONFIG_CPUCLK_266:
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cpu_rate = 266666667;
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break;
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case SYSTEM_CONFIG_CPUCLK_280:
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cpu_rate = 280000000;
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break;
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case SYSTEM_CONFIG_CPUCLK_300:
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cpu_rate = 300000000;
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break;
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}
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ralink_clk_add("cpu", cpu_rate);
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ralink_clk_add("300100.timer", cpu_rate / 2);
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ralink_clk_add("300120.watchdog", cpu_rate / 2);
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ralink_clk_add("300500.uart", cpu_rate / 2);
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ralink_clk_add("300c00.uartlite", cpu_rate / 2);
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ralink_clk_add("400000.ethernet", cpu_rate / 2);
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ralink_clk_add("480000.wmac", wmac_rate);
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}
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void __init ralink_of_remap(void)
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{
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rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc");
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rt_memc_membase = plat_of_remap_node("ralink,rt2880-memc");
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if (!rt_sysc_membase || !rt_memc_membase)
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panic("Failed to remap core resources");
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}
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void prom_soc_init(struct ralink_soc_info *soc_info)
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{
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void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT2880_SYSC_BASE);
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const char *name;
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u32 n0;
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u32 n1;
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u32 id;
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n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
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n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
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id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
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if (n0 == RT2880_CHIP_NAME0 && n1 == RT2880_CHIP_NAME1) {
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soc_info->compatible = "ralink,r2880-soc";
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name = "RT2880";
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} else {
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panic("rt288x: unknown SoC, n0:%08x n1:%08x", n0, n1);
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}
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snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
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"Ralink %s id:%u rev:%u",
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name,
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(id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
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(id & CHIP_ID_REV_MASK));
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soc_info->mem_base = RT2880_SDRAM_BASE;
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soc_info->mem_size_min = RT2880_MEM_SIZE_MIN;
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soc_info->mem_size_max = RT2880_MEM_SIZE_MAX;
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}
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