mirror of
https://github.com/FEX-Emu/linux.git
synced 2025-02-13 08:06:58 +00:00
![Pavel Pisa](/assets/img/avatar_default.png)
Only System PLL clock source is selectable by CSCR_SYSTEM_SEL bit. MPU PLL is driven by 512*CLK32 for each case. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>