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b0c568de32
Every PCI-PCI bridge window should fit inside an upstream bridge window
because orphaned address space is unreachable from the primary side of the
upstream bridge. If we inherit invalid bridge windows that overlap an
upstream window from firmware, clip them to fit and update the bridge
accordingly.
[bhelgaas: changelog]
Link: https://bugzilla.kernel.org/show_bug.cgi?id=85491
Reported-by: Marek Kordik <kordikmarek@gmail.com>
Fixes: 5b28541552
("PCI: Restrict 64-bit prefetchable bridge windows to 64-bit resources")
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: David Howells <dhowells@redhat.com>
CC: Paul Gortmaker <paul.gortmaker@windriver.com>
197 lines
6.0 KiB
C
197 lines
6.0 KiB
C
/* pci-frv.c: low-level PCI access routines
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*
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* Copyright (C) 2003-5 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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* - Derived from the i386 equivalent stuff
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/errno.h>
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#include "pci-frv.h"
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/*
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* We need to avoid collisions with `mirrored' VGA ports
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* and other strange ISA hardware, so we always want the
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* addresses to be allocated in the 0x000-0x0ff region
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* modulo 0x400.
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*
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* Why? Because some silly external IO cards only decode
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* the low 10 bits of the IO address. The 0x00-0xff region
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* is reserved for motherboard devices that decode all 16
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* bits, so it's ok to allocate at, say, 0x2800-0x28ff,
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* but we want to try to avoid allocating at 0x2900-0x2bff
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* which might have be mirrored at 0x0100-0x03ff..
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*/
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resource_size_t
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pcibios_align_resource(void *data, const struct resource *res,
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resource_size_t size, resource_size_t align)
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{
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resource_size_t start = res->start;
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if ((res->flags & IORESOURCE_IO) && (start & 0x300))
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start = (start + 0x3ff) & ~0x3ff;
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return start;
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}
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/*
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* Handle resources of PCI devices. If the world were perfect, we could
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* just allocate all the resource regions and do nothing more. It isn't.
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* On the other hand, we cannot just re-allocate all devices, as it would
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* require us to know lots of host bridge internals. So we attempt to
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* keep as much of the original configuration as possible, but tweak it
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* when it's found to be wrong.
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*
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* Known BIOS problems we have to work around:
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* - I/O or memory regions not configured
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* - regions configured, but not enabled in the command register
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* - bogus I/O addresses above 64K used
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* - expansion ROMs left enabled (this may sound harmless, but given
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* the fact the PCI specs explicitly allow address decoders to be
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* shared between expansion ROMs and other resource regions, it's
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* at least dangerous)
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*
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* Our solution:
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* (1) Allocate resources for all buses behind PCI-to-PCI bridges.
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* This gives us fixed barriers on where we can allocate.
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* (2) Allocate resources for all enabled devices. If there is
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* a collision, just mark the resource as unallocated. Also
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* disable expansion ROMs during this step.
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* (3) Try to allocate resources for disabled devices. If the
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* resources were assigned correctly, everything goes well,
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* if they weren't, they won't disturb allocation of other
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* resources.
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* (4) Assign new addresses to resources which were either
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* not configured at all or misconfigured. If explicitly
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* requested by the user, configure expansion ROM address
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* as well.
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*/
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static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
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{
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struct list_head *ln;
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struct pci_bus *bus;
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struct pci_dev *dev;
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int idx;
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struct resource *r;
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/* Depth-First Search on bus tree */
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for (ln=bus_list->next; ln != bus_list; ln=ln->next) {
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bus = list_entry(ln, struct pci_bus, node);
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if ((dev = bus->self)) {
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for (idx = PCI_BRIDGE_RESOURCES; idx < PCI_NUM_RESOURCES; idx++) {
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r = &dev->resource[idx];
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if (!r->start)
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continue;
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pci_claim_bridge_resource(dev, idx);
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}
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}
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pcibios_allocate_bus_resources(&bus->children);
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}
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}
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static void __init pcibios_allocate_resources(int pass)
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{
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struct pci_dev *dev = NULL;
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int idx, disabled;
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u16 command;
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struct resource *r;
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for_each_pci_dev(dev) {
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pci_read_config_word(dev, PCI_COMMAND, &command);
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for(idx = 0; idx < 6; idx++) {
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r = &dev->resource[idx];
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if (r->parent) /* Already allocated */
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continue;
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if (!r->start) /* Address not assigned at all */
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continue;
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if (r->flags & IORESOURCE_IO)
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disabled = !(command & PCI_COMMAND_IO);
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else
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disabled = !(command & PCI_COMMAND_MEMORY);
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if (pass == disabled) {
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DBG("PCI: Resource %08lx-%08lx (f=%lx, d=%d, p=%d)\n",
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r->start, r->end, r->flags, disabled, pass);
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if (pci_claim_resource(dev, idx) < 0) {
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/* We'll assign a new address later */
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r->end -= r->start;
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r->start = 0;
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}
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}
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}
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if (!pass) {
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r = &dev->resource[PCI_ROM_RESOURCE];
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if (r->flags & IORESOURCE_ROM_ENABLE) {
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/* Turn the ROM off, leave the resource region, but keep it unregistered. */
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u32 reg;
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DBG("PCI: Switching off ROM of %s\n", pci_name(dev));
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r->flags &= ~IORESOURCE_ROM_ENABLE;
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pci_read_config_dword(dev, dev->rom_base_reg, ®);
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pci_write_config_dword(dev, dev->rom_base_reg, reg & ~PCI_ROM_ADDRESS_ENABLE);
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}
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}
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}
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}
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static void __init pcibios_assign_resources(void)
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{
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struct pci_dev *dev = NULL;
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int idx;
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struct resource *r;
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for_each_pci_dev(dev) {
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int class = dev->class >> 8;
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/* Don't touch classless devices and host bridges */
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if (!class || class == PCI_CLASS_BRIDGE_HOST)
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continue;
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for(idx=0; idx<6; idx++) {
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r = &dev->resource[idx];
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/*
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* Don't touch IDE controllers and I/O ports of video cards!
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*/
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if ((class == PCI_CLASS_STORAGE_IDE && idx < 4) ||
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(class == PCI_CLASS_DISPLAY_VGA && (r->flags & IORESOURCE_IO)))
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continue;
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/*
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* We shall assign a new address to this resource, either because
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* the BIOS forgot to do so or because we have decided the old
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* address was unusable for some reason.
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*/
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if (!r->start && r->end)
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pci_assign_resource(dev, idx);
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}
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if (pci_probe & PCI_ASSIGN_ROMS) {
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r = &dev->resource[PCI_ROM_RESOURCE];
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r->end -= r->start;
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r->start = 0;
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if (r->end)
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pci_assign_resource(dev, PCI_ROM_RESOURCE);
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}
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}
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}
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void __init pcibios_resource_survey(void)
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{
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DBG("PCI: Allocating resources\n");
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pcibios_allocate_bus_resources(&pci_root_buses);
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pcibios_allocate_resources(0);
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pcibios_allocate_resources(1);
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pcibios_assign_resources();
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}
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