Doug Anderson 221dfbae2b clk: rockchip: Add CLK_SET_RATE_PARENT to sclk_uart clocks ...

We'd like to be able to set the clock rate of the sclk_uart clocks and
actually be able to achieve clock rates greater than 24MHz.  To do
this we need to be able to pass rate changes upward.

Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

2014-12-21 14:15:26 +01:00

..

clk-cpu.c

clk: rockchip: add new clock-type for the cpuclk

2014-09-27 17:57:41 +02:00

clk-mmc-phase.c

clk: rockchip: Add support for the mmc clock phases using the framework

2014-11-28 00:44:24 +01:00

clk-pll.c

clk: rockchip: add optional sync to pll rate parameters

2014-11-25 09:57:18 +01:00

clk-rk3188.c

clk: rockchip: add ROCKCHIP_PLL_SYNC_RATE flag to some plls

2014-11-25 09:57:22 +01:00

clk-rk3288.c

clk: rockchip: Add CLK_SET_RATE_PARENT to sclk_uart clocks

2014-12-21 14:15:26 +01:00

clk-rockchip.c

…

clk.c

- clock phase setting capability for the rk3288 mmc clocks

2014-11-28 21:00:16 -08:00

clk.h

clk: rockchip: Add support for the mmc clock phases using the framework

2014-11-28 00:44:24 +01:00

Makefile

clk: rockchip: Add support for the mmc clock phases using the framework

2014-11-28 00:44:24 +01:00

softrst.c

clk: rockchip: add reset controller

2014-07-13 12:17:07 -07:00