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S5PC100 has 4 PLLs (APLL,MPLL,EPLL,HPLL) and 3 clock domains. Clock scheme is implemented here. Signed-off-by: Byungho Min <bhmin@samsung.com> [ben-linux@fluff.org: edited title] Signed-off-by: Ben Dooks <ben-linux@fluff.org>
39 lines
1.0 KiB
C
39 lines
1.0 KiB
C
/* arch/arm/plat-s5pc1xx/include/plat/pll.h
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*
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* Copyright 2009 Samsung Electronics Co.
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* Byungho Min <bhmin@samsung.com>
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*
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* S5PC1XX PLL code
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*
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* Based on plat-s3c64xx/include/plat/pll.h
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#define S5P_PLL_MDIV_MASK ((1 << (25-16+1)) - 1)
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#define S5P_PLL_PDIV_MASK ((1 << (13-8+1)) - 1)
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#define S5P_PLL_SDIV_MASK ((1 << (2-0+1)) - 1)
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#define S5P_PLL_MDIV_SHIFT (16)
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#define S5P_PLL_PDIV_SHIFT (8)
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#define S5P_PLL_SDIV_SHIFT (0)
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#include <asm/div64.h>
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static inline unsigned long s5pc1xx_get_pll(unsigned long baseclk,
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u32 pllcon)
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{
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u32 mdiv, pdiv, sdiv;
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u64 fvco = baseclk;
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mdiv = (pllcon >> S5P_PLL_MDIV_SHIFT) & S5P_PLL_MDIV_MASK;
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pdiv = (pllcon >> S5P_PLL_PDIV_SHIFT) & S5P_PLL_PDIV_MASK;
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sdiv = (pllcon >> S5P_PLL_SDIV_SHIFT) & S5P_PLL_SDIV_MASK;
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fvco *= mdiv;
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do_div(fvco, (pdiv << sdiv));
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return (unsigned long)fvco;
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}
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