Lennert Buytenhek 81600eea98 mv643xx_eth: use auto phy polling for configuring (R)(G)MII interface ... The mv643xx_eth hardware has a provision for polling the PHY's MII management registers to obtain the (R)(G)MII interface speed (10/100/1000) and duplex (half/full) and pause (off/symmetric) settings to use to talk to the PHY. The driver currently does not make use of this feature. Instead, whenever there is a link status change event, it reads the current link parameters from the PHY, and programs those parameters into the mv643xx_eth MAC by hand. This patch switches the mv643xx_eth driver to letting the MAC auto-determine the (R)(G)MII link parameters by PHY polling, if there is a PHY present. For PHYless ports (when e.g. the (R)(G)MII interface is connected to a hardware switch), we keep hardcoding the MII interface parameters. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>		2008-07-24 06:22:59 +02:00
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addr-map.c
common.c	[ARM] Kirkwood: support L2 writeback mode	2008-06-30 14:25:24 -04:00
common.h
db88f6281-bp-setup.c
irq.c
Kconfig
Makefile
Makefile.boot
pcie.c
rd88f6192-nas-setup.c
rd88f6281-setup.c	mv643xx_eth: use auto phy polling for configuring (R)(G)MII interface	2008-07-24 06:22:59 +02:00