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1e4d2d3da3
The 6282 SoC is compatible to 6280 and features faster CPU, DDR3, additional PCIe interface, and LCD controller. More information can be found here: http://www.marvell.com/products/processors/embedded/armada_300/armada_310.pdf Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
102 lines
2.3 KiB
C
102 lines
2.3 KiB
C
/*
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* arch/arm/mach-kirkwood/mpp.c
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*
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* MPP functions for Marvell Kirkwood SoCs
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/mbus.h>
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#include <linux/io.h>
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#include <asm/gpio.h>
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#include <mach/hardware.h>
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#include "common.h"
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#include "mpp.h"
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static unsigned int __init kirkwood_variant(void)
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{
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u32 dev, rev;
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kirkwood_pcie_id(&dev, &rev);
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if ((dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0) ||
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(dev == MV88F6282_DEV_ID))
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return MPP_F6281_MASK;
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if (dev == MV88F6192_DEV_ID && rev >= MV88F6192_REV_A0)
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return MPP_F6192_MASK;
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if (dev == MV88F6180_DEV_ID)
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return MPP_F6180_MASK;
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printk(KERN_ERR "MPP setup: unknown kirkwood variant "
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"(dev %#x rev %#x)\n", dev, rev);
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return 0;
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}
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#define MPP_CTRL(i) (DEV_BUS_VIRT_BASE + (i) * 4)
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#define MPP_NR_REGS (1 + MPP_MAX/8)
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void __init kirkwood_mpp_conf(unsigned int *mpp_list)
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{
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u32 mpp_ctrl[MPP_NR_REGS];
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unsigned int variant_mask;
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int i;
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variant_mask = kirkwood_variant();
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if (!variant_mask)
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return;
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/* Initialize gpiolib. */
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orion_gpio_init();
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printk(KERN_DEBUG "initial MPP regs:");
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for (i = 0; i < MPP_NR_REGS; i++) {
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mpp_ctrl[i] = readl(MPP_CTRL(i));
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printk(" %08x", mpp_ctrl[i]);
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}
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printk("\n");
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while (*mpp_list) {
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unsigned int num = MPP_NUM(*mpp_list);
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unsigned int sel = MPP_SEL(*mpp_list);
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int shift, gpio_mode;
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if (num > MPP_MAX) {
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printk(KERN_ERR "kirkwood_mpp_conf: invalid MPP "
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"number (%u)\n", num);
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continue;
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}
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if (!(*mpp_list & variant_mask)) {
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printk(KERN_WARNING
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"kirkwood_mpp_conf: requested MPP%u config "
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"unavailable on this hardware\n", num);
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continue;
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}
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shift = (num & 7) << 2;
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mpp_ctrl[num / 8] &= ~(0xf << shift);
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mpp_ctrl[num / 8] |= sel << shift;
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gpio_mode = 0;
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if (*mpp_list & MPP_INPUT_MASK)
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gpio_mode |= GPIO_INPUT_OK;
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if (*mpp_list & MPP_OUTPUT_MASK)
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gpio_mode |= GPIO_OUTPUT_OK;
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if (sel != 0)
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gpio_mode = 0;
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orion_gpio_set_valid(num, gpio_mode);
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mpp_list++;
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}
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printk(KERN_DEBUG " final MPP regs:");
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for (i = 0; i < MPP_NR_REGS; i++) {
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writel(mpp_ctrl[i], MPP_CTRL(i));
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printk(" %08x", mpp_ctrl[i]);
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}
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printk("\n");
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}
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