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9ffa739606
This patch adds support for the other three palette formats possible with
the PXA LCD controller. This is required on boards where an LCD is connected
with all its 18 bits. With this patch, it's possible to use an 8-bit mode
with 18-bit palette entries. This used to be possible in 2.4 kernels but
disappeared in 2.6. With current kernels, you can only get wrong colours
out of an LCD connected this way.
Users can choose the palette format by doing something like this
in their board definition:
static struct pxafb_mach_info my_fb_info = {
[...]
.lccr3 = LCCR3_OutEnH | LCCR3_PixFlEdg | LCCR3_PDFOR_3,
.lccr4 = LCCR4_PAL_FOR_2,
[...]
};
Signed-off-by: Hans J. Koch <hjk@linutronix.de>
Signed-off-by: Antonino Daplas <adaplas@gmail.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
122 lines
2.8 KiB
C
122 lines
2.8 KiB
C
#ifndef __PXAFB_H__
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#define __PXAFB_H__
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/*
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* linux/drivers/video/pxafb.h
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* -- Intel PXA250/210 LCD Controller Frame Buffer Device
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*
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* Copyright (C) 1999 Eric A. Thomas.
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* Copyright (C) 2004 Jean-Frederic Clere.
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* Copyright (C) 2004 Ian Campbell.
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* Copyright (C) 2004 Jeff Lackey.
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* Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
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* which in turn is
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* Based on acornfb.c Copyright (C) Russell King.
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*
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* 2001-08-03: Cliff Brake <cbrake@acclent.com>
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* - ported SA1100 code to PXA
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive
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* for more details.
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*/
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/* Shadows for LCD controller registers */
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struct pxafb_lcd_reg {
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unsigned int lccr0;
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unsigned int lccr1;
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unsigned int lccr2;
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unsigned int lccr3;
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};
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/* PXA LCD DMA descriptor */
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struct pxafb_dma_descriptor {
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unsigned int fdadr;
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unsigned int fsadr;
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unsigned int fidr;
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unsigned int ldcmd;
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};
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struct pxafb_info {
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struct fb_info fb;
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struct device *dev;
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struct clk *clk;
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/*
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* These are the addresses we mapped
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* the framebuffer memory region to.
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*/
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/* raw memory addresses */
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dma_addr_t map_dma; /* physical */
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u_char * map_cpu; /* virtual */
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u_int map_size;
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/* addresses of pieces placed in raw buffer */
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u_char * screen_cpu; /* virtual address of frame buffer */
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dma_addr_t screen_dma; /* physical address of frame buffer */
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u16 * palette_cpu; /* virtual address of palette memory */
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dma_addr_t palette_dma; /* physical address of palette memory */
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u_int palette_size;
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/* DMA descriptors */
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struct pxafb_dma_descriptor * dmadesc_fblow_cpu;
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dma_addr_t dmadesc_fblow_dma;
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struct pxafb_dma_descriptor * dmadesc_fbhigh_cpu;
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dma_addr_t dmadesc_fbhigh_dma;
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struct pxafb_dma_descriptor * dmadesc_palette_cpu;
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dma_addr_t dmadesc_palette_dma;
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dma_addr_t fdadr0;
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dma_addr_t fdadr1;
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u_int lccr0;
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u_int lccr3;
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u_int lccr4;
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u_int cmap_inverse:1,
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cmap_static:1,
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unused:30;
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u_int reg_lccr0;
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u_int reg_lccr1;
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u_int reg_lccr2;
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u_int reg_lccr3;
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u_int reg_lccr4;
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unsigned long hsync_time;
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volatile u_char state;
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volatile u_char task_state;
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struct semaphore ctrlr_sem;
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wait_queue_head_t ctrlr_wait;
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struct work_struct task;
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#ifdef CONFIG_CPU_FREQ
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struct notifier_block freq_transition;
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struct notifier_block freq_policy;
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#endif
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};
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#define TO_INF(ptr,member) container_of(ptr,struct pxafb_info,member)
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/*
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* These are the actions for set_ctrlr_state
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*/
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#define C_DISABLE (0)
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#define C_ENABLE (1)
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#define C_DISABLE_CLKCHANGE (2)
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#define C_ENABLE_CLKCHANGE (3)
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#define C_REENABLE (4)
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#define C_DISABLE_PM (5)
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#define C_ENABLE_PM (6)
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#define C_STARTUP (7)
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#define PXA_NAME "PXA"
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/*
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* Minimum X and Y resolutions
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*/
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#define MIN_XRES 64
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#define MIN_YRES 64
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#endif /* __PXAFB_H__ */
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