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The Qualcomm NAND controller is found in SoCs like IPQ806x, MSM7xx, MDM9x15 series. It exists as a sub block inside the IPs EBI2 (External Bus Interface 2) and QPIC (Qualcomm Parallel Interface Controller). These IPs provide a broader interface for external slow peripheral devices such as LCD and NAND/NOR flash memory or SRAM like interfaces. We add support for the NAND controller found within EBI2. For the SoCs of our interest, we only use the NAND controller within EBI2. Therefore, it's safe for us to assume that the NAND controller is a standalone block within the SoC. The controller supports 512B, 2kB, 4kB and 8kB page 8-bit and 16-bit NAND flash devices. It contains a HW ECC block that supports BCH ECC (4, 8 and 16 bit correction/step) and RS ECC(4 bit correction/step) that covers main and spare data. The controller contains an internal 512 byte page buffer to which we read/write via DMA. The EBI2 type NAND controller uses ADM DMA for register read/write and data transfers. The controller performs page reads and writes at a codeword/step level of 512 bytes. It can support up to 2 external chips of different configurations. The driver prepares register read and write configuration descriptors for each codeword, followed by data descriptors to read or write data from the controller's internal buffer. It uses a single ADM DMA channel that we get via dmaengine API. The controller requires 2 ADM CRCIs for command and data flow control. These are passed via DT. The ecc layout used by the controller is syndrome like, but we can't use the standard syndrome ecc ops because of several reasons. First, the amount of data bytes covered by ecc isn't same in each step. Second, writing to free oob space requires us writing to the entire step in which the oob lies. This forces us to create our own ecc ops. One more difference is how the controller accesses the bad block marker. The controller ignores reading the marker when ECC is enabled. ECC needs to be explicity disabled to read or write to the bad block marker. The nand_bbt helpers library hence can't access BBMs for the controller. For now, we skip the creation of BBT and populate chip->block_bad and chip->block_markbad helpers instead. Reviewed-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
62 lines
2.5 KiB
Makefile
62 lines
2.5 KiB
Makefile
#
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# linux/drivers/nand/Makefile
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#
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obj-$(CONFIG_MTD_NAND) += nand.o
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obj-$(CONFIG_MTD_NAND_ECC) += nand_ecc.o
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obj-$(CONFIG_MTD_NAND_BCH) += nand_bch.o
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obj-$(CONFIG_MTD_NAND_IDS) += nand_ids.o
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obj-$(CONFIG_MTD_SM_COMMON) += sm_common.o
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obj-$(CONFIG_MTD_NAND_CAFE) += cafe_nand.o
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obj-$(CONFIG_MTD_NAND_AMS_DELTA) += ams-delta.o
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obj-$(CONFIG_MTD_NAND_DENALI) += denali.o
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obj-$(CONFIG_MTD_NAND_DENALI_PCI) += denali_pci.o
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obj-$(CONFIG_MTD_NAND_DENALI_DT) += denali_dt.o
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obj-$(CONFIG_MTD_NAND_AU1550) += au1550nd.o
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obj-$(CONFIG_MTD_NAND_BF5XX) += bf5xx_nand.o
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obj-$(CONFIG_MTD_NAND_S3C2410) += s3c2410.o
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obj-$(CONFIG_MTD_NAND_DAVINCI) += davinci_nand.o
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obj-$(CONFIG_MTD_NAND_DISKONCHIP) += diskonchip.o
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obj-$(CONFIG_MTD_NAND_DOCG4) += docg4.o
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obj-$(CONFIG_MTD_NAND_FSMC) += fsmc_nand.o
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obj-$(CONFIG_MTD_NAND_SHARPSL) += sharpsl.o
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obj-$(CONFIG_MTD_NAND_NANDSIM) += nandsim.o
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obj-$(CONFIG_MTD_NAND_CS553X) += cs553x_nand.o
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obj-$(CONFIG_MTD_NAND_NDFC) += ndfc.o
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obj-$(CONFIG_MTD_NAND_ATMEL) += atmel_nand.o
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obj-$(CONFIG_MTD_NAND_GPIO) += gpio.o
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omap2_nand-objs := omap2.o
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obj-$(CONFIG_MTD_NAND_OMAP2) += omap2_nand.o
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obj-$(CONFIG_MTD_NAND_OMAP_BCH_BUILD) += omap_elm.o
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obj-$(CONFIG_MTD_NAND_CM_X270) += cmx270_nand.o
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obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o
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obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o
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obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
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obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o
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obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o
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obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc_nand.o
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obj-$(CONFIG_MTD_NAND_FSL_IFC) += fsl_ifc_nand.o
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obj-$(CONFIG_MTD_NAND_FSL_UPM) += fsl_upm.o
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obj-$(CONFIG_MTD_NAND_SLC_LPC32XX) += lpc32xx_slc.o
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obj-$(CONFIG_MTD_NAND_MLC_LPC32XX) += lpc32xx_mlc.o
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obj-$(CONFIG_MTD_NAND_SH_FLCTL) += sh_flctl.o
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obj-$(CONFIG_MTD_NAND_MXC) += mxc_nand.o
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obj-$(CONFIG_MTD_NAND_SOCRATES) += socrates_nand.o
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obj-$(CONFIG_MTD_NAND_TXX9NDFMC) += txx9ndfmc.o
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obj-$(CONFIG_MTD_NAND_NUC900) += nuc900_nand.o
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obj-$(CONFIG_MTD_NAND_MPC5121_NFC) += mpc5121_nfc.o
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obj-$(CONFIG_MTD_NAND_VF610_NFC) += vf610_nfc.o
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obj-$(CONFIG_MTD_NAND_RICOH) += r852.o
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obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o
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obj-$(CONFIG_MTD_NAND_JZ4780) += jz4780_nand.o jz4780_bch.o
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obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/
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obj-$(CONFIG_MTD_NAND_XWAY) += xway_nand.o
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obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/
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obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_nand.o
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obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o
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obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/
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obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o
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nand-objs := nand_base.o nand_bbt.o nand_timings.o
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