Viresh Kumar 270b9f421e SPEAr: clk: Add Fractional Synthesizer clock ...

All SPEAr SoC's contain Fractional Synthesizers. Their Fout is derived from
following equations:

Fout = Fin / (2 * div) (division factor)
div is 17 bits:-
     0-13 (fractional part)
     14-16 (integer part)
     div is (16-14 bits).(13-0 bits) (in binary)

     Fout = Fin/(2 * div)
     Fout = ((Fin / 10000)/(2 * div)) * 10000
     Fout = (2^14 * (Fin / 10000)/(2^14 * (2 * div))) * 10000
     Fout = (((Fin / 10000) << 14)/(2 * (div << 14))) * 10000

div << 14 is simply 17 bit value written at register.

This patch adds in support for this type of clock.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>

2012-05-12 21:19:27 +02:00

..

spear

SPEAr: clk: Add Fractional Synthesizer clock

2012-05-12 21:19:27 +02:00

clk-divider.c

clk: Use a separate struct for holding init data.

2012-05-01 18:13:20 -07:00

clk-fixed-factor.c

clk: add a fixed factor clock

2012-05-08 14:13:25 -07:00

clk-fixed-rate.c

clk: Use a separate struct for holding init data.

2012-05-01 18:13:20 -07:00

clk-gate.c

clk: Use a separate struct for holding init data.

2012-05-01 18:13:20 -07:00

clk-mux.c

clk: mux: assign init data

2012-05-08 14:13:07 -07:00

clk.c

clk: remove COMMON_CLK_DISABLE_UNUSED

2012-05-08 14:12:42 -07:00

clkdev.c

CLKDEV: provide helpers for common clock framework

2012-05-02 09:30:32 +01:00

Kconfig

clk: remove COMMON_CLK_DISABLE_UNUSED

2012-05-08 14:12:42 -07:00

Makefile

SPEAr: clk: Add VCO-PLL Synthesizer clock

2012-05-12 21:19:23 +02:00