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273b72c8ce
PXA's SSP engine fails to take its current channel phase into account when enabling a stream while the engine is already running. This results in randomly swapped left/right channels on either the record or the playback side, depending on which one was enabled first. The following patch fixes this by factoring out the bit field modifications in question to a separate function that pauses the engine temporarily, modifies the bits and kicks it off again afterwards. Appearantly, a transition of SSCR0_SSE syncs both directions properly. The patch has been rolled out to quite a number of devices over the last weeks and seems to fix the issue reliably. Signed-off-by: Daniel Mack <zonque@gmail.com> Reported-and-tested-by: Sven Neumann <s.neumann@raumfeld.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Cc: stable@vger.kernel.org |
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| imx | ||
| jz4740 | ||
| kirkwood | ||
| mid-x86 | ||
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| Makefile | ||
| soc-cache.c | ||
| soc-core.c | ||
| soc-dapm.c | ||
| soc-dmaengine-pcm.c | ||
| soc-io.c | ||
| soc-jack.c | ||
| soc-pcm.c | ||
| soc-utils.c | ||