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12b8eb8652
This allows us to determine the irq controller base address on runtime. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
53 lines
1.3 KiB
ArmAsm
53 lines
1.3 KiB
ArmAsm
/*
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* Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org>
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* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <mach/hardware.h>
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#define AVIC_NIMASK 0x04
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@ this macro disables fast irq (not implemented)
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.macro disable_fiq
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.endm
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.macro get_irqnr_preamble, base, tmp
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ldr \base, =avic_base
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ldr \base, [\base]
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#ifdef CONFIG_MXC_IRQ_PRIOR
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ldr r4, [\base, #AVIC_NIMASK]
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#endif
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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@ this macro checks which interrupt occured
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@ and returns its number in irqnr
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@ and returns if an interrupt occured in irqstat
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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@ Load offset & priority of the highest priority
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@ interrupt pending from AVIC_NIVECSR
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ldr \irqstat, [\base, #0x40]
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@ Shift to get the decoded IRQ number, using ASR so
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@ 'no interrupt pending' becomes 0xffffffff
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mov \irqnr, \irqstat, asr #16
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@ set zero flag if IRQ + 1 == 0
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adds \tmp, \irqnr, #1
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#ifdef CONFIG_MXC_IRQ_PRIOR
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bicne \tmp, \irqstat, #0xFFFFFFE0
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strne \tmp, [\base, #AVIC_NIMASK]
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streq r4, [\base, #AVIC_NIMASK]
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#endif
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.endm
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@ irq priority table (not used)
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.macro irq_prio_table
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.endm
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