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4f683a046c
The old names are still defined using the new names. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
76 lines
2.7 KiB
C
76 lines
2.7 KiB
C
/*
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* IRAM
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*/
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#define MX31_IRAM_BASE_ADDR 0x1ffc0000 /* internal ram */
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#define MX31_IRAM_SIZE SZ_16K
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#define MX31_OTG_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x88000)
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#define MX31_ATA_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x8c000)
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#define MX31_UART4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xb0000)
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#define MX31_UART5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xb4000)
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#define MX31_MMC_SDHC1_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x04000)
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#define MX31_MMC_SDHC2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x08000)
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#define MX31_SIM1_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x18000)
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#define MX31_IIM_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x1c000)
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#define MX31_CSPI3_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x84000)
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#define MX31_FIRI_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x8c000)
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#define MX31_SCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xae000)
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#define MX31_SMN_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xaf000)
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#define MX31_MPEG4_ENC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc8000)
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#define MX31_NFC_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x0000)
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#define MX31_INT_MPEG4_ENCODER 5
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#define MX31_INT_FIRI 7
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#define MX31_INT_MMC_SDHC2 8
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#define MX31_INT_MMC_SDHC1 9
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#define MX31_INT_SSI2 11
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#define MX31_INT_SSI1 12
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#define MX31_INT_MBX 16
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#define MX31_INT_CSPI3 17
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#define MX31_INT_SIM2 20
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#define MX31_INT_SIM1 21
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#define MX31_INT_CCM_DVFS 31
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#define MX31_INT_USB1 35
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#define MX31_INT_USB2 36
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#define MX31_INT_USB3 37
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#define MX31_INT_USB4 38
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#define MX31_INT_MSHC2 40
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#define MX31_INT_UART4 46
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#define MX31_INT_UART5 47
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#define MX31_INT_CCM 53
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#define MX31_INT_PCMCIA 54
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/* these should go away */
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#define ATA_BASE_ADDR MX31_ATA_BASE_ADDR
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#define UART4_BASE_ADDR MX31_UART4_BASE_ADDR
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#define UART5_BASE_ADDR MX31_UART5_BASE_ADDR
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#define MMC_SDHC1_BASE_ADDR MX31_MMC_SDHC1_BASE_ADDR
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#define MMC_SDHC2_BASE_ADDR MX31_MMC_SDHC2_BASE_ADDR
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#define SIM1_BASE_ADDR MX31_SIM1_BASE_ADDR
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#define IIM_BASE_ADDR MX31_IIM_BASE_ADDR
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#define CSPI3_BASE_ADDR MX31_CSPI3_BASE_ADDR
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#define FIRI_BASE_ADDR MX31_FIRI_BASE_ADDR
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#define SCM_BASE_ADDR MX31_SCM_BASE_ADDR
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#define SMN_BASE_ADDR MX31_SMN_BASE_ADDR
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#define MPEG4_ENC_BASE_ADDR MX31_MPEG4_ENC_BASE_ADDR
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#define MXC_INT_MPEG4_ENCODER MX31_INT_MPEG4_ENCODER
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#define MXC_INT_FIRI MX31_INT_FIRI
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#define MXC_INT_MMC_SDHC1 MX31_INT_MMC_SDHC1
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#define MXC_INT_MBX MX31_INT_MBX
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#define MXC_INT_CSPI3 MX31_INT_CSPI3
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#define MXC_INT_SIM2 MX31_INT_SIM2
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#define MXC_INT_SIM1 MX31_INT_SIM1
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#define MXC_INT_CCM_DVFS MX31_INT_CCM_DVFS
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#define MXC_INT_USB1 MX31_INT_USB1
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#define MXC_INT_USB2 MX31_INT_USB2
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#define MXC_INT_USB3 MX31_INT_USB3
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#define MXC_INT_USB4 MX31_INT_USB4
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#define MXC_INT_MSHC2 MX31_INT_MSHC2
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#define MXC_INT_UART4 MX31_INT_UART4
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#define MXC_INT_UART5 MX31_INT_UART5
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#define MXC_INT_CCM MX31_INT_CCM
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#define MXC_INT_PCMCIA MX31_INT_PCMCIA
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