David Daney 6f329468f3 MIPS: Give Octeon+ CPUs their own cputype. ...

This allows us to treat them differently at runtime.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/951/
Patchwork: http://patchwork.linux-mips.org/patch/987/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

2010-02-27 12:53:26 +01:00

..

c-octeon.c

MIPS: Give Octeon+ CPUs their own cputype.

2010-02-27 12:53:26 +01:00

c-r3k.c

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c-r4k.c

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c-tx39.c

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cache.c

MIPS: Implement Read Inhibit/eXecute Inhibit

2010-02-27 12:53:26 +01:00

cerr-sb1.c

MIPS: Sibyte: Use hweight8 instead of counting bits

2009-12-17 01:57:16 +00:00

cex-gen.S

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cex-oct.S

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cex-sb1.S

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dma-default.c

MIPS: Add DMA declare coherent memory support

2009-11-13 18:10:37 +01:00

extable.c

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fault.c

MIPS: Implement Read Inhibit/eXecute Inhibit

2010-02-27 12:53:26 +01:00

highmem.c

MIPS: Highmem: Fix build error

2010-02-22 21:42:11 +01:00

hugetlbpage.c

MIPS: Nuke trailing blank lines

2010-02-27 12:53:14 +01:00

init.c

MIPS: Implement Read Inhibit/eXecute Inhibit

2010-02-27 12:53:26 +01:00

ioremap.c

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Makefile

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page.c

MIPS: Move arch/mips/mm/uasm.h to arch/mips/include/asm/uasm.h

2010-02-27 12:53:19 +01:00

pgtable-32.c

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pgtable-64.c

MIPS: Two-level pagetables for 64-bit kernels with 64KB pages.

2010-02-27 12:53:03 +01:00

sc-ip22.c

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sc-mips.c

MIPS: MIPSxx SC: Avoid destructive invalidation on partial L2 cachelines.

2009-09-30 21:47:00 +02:00

sc-r5k.c

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sc-rm7k.c

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tlb-r3k.c

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tlb-r4k.c

MIPS: Implement Read Inhibit/eXecute Inhibit

2010-02-27 12:53:26 +01:00

tlb-r8k.c

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tlbex-fault.S

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tlbex.c

MIPS: Implement Read Inhibit/eXecute Inhibit

2010-02-27 12:53:26 +01:00

uasm.c

MIPS: Add TLBR and ROTR to uasm.

2010-02-27 12:53:25 +01:00