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Fix various grammatical issues in Documentation/memory-barriers.txt. Cc: "Robert P. J. Day" <rpjday@mindspring.com> Signed-off-by: Jarek Poplawski <jarkao2@o2.pl> Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2137 lines
75 KiB
Plaintext
2137 lines
75 KiB
Plaintext
============================
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LINUX KERNEL MEMORY BARRIERS
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============================
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By: David Howells <dhowells@redhat.com>
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Contents:
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(*) Abstract memory access model.
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- Device operations.
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- Guarantees.
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(*) What are memory barriers?
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- Varieties of memory barrier.
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- What may not be assumed about memory barriers?
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- Data dependency barriers.
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- Control dependencies.
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- SMP barrier pairing.
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- Examples of memory barrier sequences.
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- Read memory barriers vs load speculation.
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(*) Explicit kernel barriers.
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- Compiler barrier.
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- CPU memory barriers.
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- MMIO write barrier.
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(*) Implicit kernel memory barriers.
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- Locking functions.
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- Interrupt disabling functions.
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- Miscellaneous functions.
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(*) Inter-CPU locking barrier effects.
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- Locks vs memory accesses.
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- Locks vs I/O accesses.
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(*) Where are memory barriers needed?
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- Interprocessor interaction.
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- Atomic operations.
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- Accessing devices.
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- Interrupts.
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(*) Kernel I/O barrier effects.
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(*) Assumed minimum execution ordering model.
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(*) The effects of the cpu cache.
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- Cache coherency.
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- Cache coherency vs DMA.
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- Cache coherency vs MMIO.
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(*) The things CPUs get up to.
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- And then there's the Alpha.
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(*) References.
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============================
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ABSTRACT MEMORY ACCESS MODEL
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============================
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Consider the following abstract model of the system:
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: :
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: :
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: :
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+-------+ : +--------+ : +-------+
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| | : | | : | |
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| | : | | : | |
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| CPU 1 |<----->| Memory |<----->| CPU 2 |
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| | : | | : | |
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| | : | | : | |
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+-------+ : +--------+ : +-------+
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^ : ^ : ^
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| : | : |
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| : | : |
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| : v : |
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| : +--------+ : |
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| : | | : |
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| : | | : |
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+---------->| Device |<----------+
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: | | :
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: | | :
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: +--------+ :
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: :
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Each CPU executes a program that generates memory access operations. In the
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abstract CPU, memory operation ordering is very relaxed, and a CPU may actually
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perform the memory operations in any order it likes, provided program causality
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appears to be maintained. Similarly, the compiler may also arrange the
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instructions it emits in any order it likes, provided it doesn't affect the
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apparent operation of the program.
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So in the above diagram, the effects of the memory operations performed by a
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CPU are perceived by the rest of the system as the operations cross the
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interface between the CPU and rest of the system (the dotted lines).
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For example, consider the following sequence of events:
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CPU 1 CPU 2
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=============== ===============
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{ A == 1; B == 2 }
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A = 3; x = A;
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B = 4; y = B;
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The set of accesses as seen by the memory system in the middle can be arranged
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in 24 different combinations:
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STORE A=3, STORE B=4, x=LOAD A->3, y=LOAD B->4
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STORE A=3, STORE B=4, y=LOAD B->4, x=LOAD A->3
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STORE A=3, x=LOAD A->3, STORE B=4, y=LOAD B->4
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STORE A=3, x=LOAD A->3, y=LOAD B->2, STORE B=4
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STORE A=3, y=LOAD B->2, STORE B=4, x=LOAD A->3
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STORE A=3, y=LOAD B->2, x=LOAD A->3, STORE B=4
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STORE B=4, STORE A=3, x=LOAD A->3, y=LOAD B->4
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STORE B=4, ...
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...
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and can thus result in four different combinations of values:
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x == 1, y == 2
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x == 1, y == 4
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x == 3, y == 2
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x == 3, y == 4
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Furthermore, the stores committed by a CPU to the memory system may not be
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perceived by the loads made by another CPU in the same order as the stores were
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committed.
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As a further example, consider this sequence of events:
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CPU 1 CPU 2
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=============== ===============
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{ A == 1, B == 2, C = 3, P == &A, Q == &C }
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B = 4; Q = P;
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P = &B D = *Q;
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There is an obvious data dependency here, as the value loaded into D depends on
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the address retrieved from P by CPU 2. At the end of the sequence, any of the
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following results are possible:
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(Q == &A) and (D == 1)
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(Q == &B) and (D == 2)
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(Q == &B) and (D == 4)
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Note that CPU 2 will never try and load C into D because the CPU will load P
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into Q before issuing the load of *Q.
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DEVICE OPERATIONS
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-----------------
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Some devices present their control interfaces as collections of memory
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locations, but the order in which the control registers are accessed is very
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important. For instance, imagine an ethernet card with a set of internal
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registers that are accessed through an address port register (A) and a data
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port register (D). To read internal register 5, the following code might then
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be used:
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*A = 5;
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x = *D;
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but this might show up as either of the following two sequences:
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STORE *A = 5, x = LOAD *D
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x = LOAD *D, STORE *A = 5
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the second of which will almost certainly result in a malfunction, since it set
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the address _after_ attempting to read the register.
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GUARANTEES
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----------
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There are some minimal guarantees that may be expected of a CPU:
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(*) On any given CPU, dependent memory accesses will be issued in order, with
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respect to itself. This means that for:
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Q = P; D = *Q;
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the CPU will issue the following memory operations:
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Q = LOAD P, D = LOAD *Q
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and always in that order.
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(*) Overlapping loads and stores within a particular CPU will appear to be
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ordered within that CPU. This means that for:
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a = *X; *X = b;
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the CPU will only issue the following sequence of memory operations:
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a = LOAD *X, STORE *X = b
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And for:
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*X = c; d = *X;
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the CPU will only issue:
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STORE *X = c, d = LOAD *X
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(Loads and stores overlap if they are targeted at overlapping pieces of
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memory).
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And there are a number of things that _must_ or _must_not_ be assumed:
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(*) It _must_not_ be assumed that independent loads and stores will be issued
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in the order given. This means that for:
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X = *A; Y = *B; *D = Z;
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we may get any of the following sequences:
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X = LOAD *A, Y = LOAD *B, STORE *D = Z
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X = LOAD *A, STORE *D = Z, Y = LOAD *B
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Y = LOAD *B, X = LOAD *A, STORE *D = Z
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Y = LOAD *B, STORE *D = Z, X = LOAD *A
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STORE *D = Z, X = LOAD *A, Y = LOAD *B
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STORE *D = Z, Y = LOAD *B, X = LOAD *A
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(*) It _must_ be assumed that overlapping memory accesses may be merged or
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discarded. This means that for:
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X = *A; Y = *(A + 4);
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we may get any one of the following sequences:
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X = LOAD *A; Y = LOAD *(A + 4);
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Y = LOAD *(A + 4); X = LOAD *A;
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{X, Y} = LOAD {*A, *(A + 4) };
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And for:
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*A = X; Y = *A;
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we may get either of:
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STORE *A = X; Y = LOAD *A;
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STORE *A = Y = X;
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=========================
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WHAT ARE MEMORY BARRIERS?
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=========================
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As can be seen above, independent memory operations are effectively performed
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in random order, but this can be a problem for CPU-CPU interaction and for I/O.
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What is required is some way of intervening to instruct the compiler and the
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CPU to restrict the order.
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Memory barriers are such interventions. They impose a perceived partial
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ordering over the memory operations on either side of the barrier.
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Such enforcement is important because the CPUs and other devices in a system
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can use a variety of tricks to improve performance, including reordering,
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deferral and combination of memory operations; speculative loads; speculative
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branch prediction and various types of caching. Memory barriers are used to
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override or suppress these tricks, allowing the code to sanely control the
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interaction of multiple CPUs and/or devices.
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VARIETIES OF MEMORY BARRIER
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---------------------------
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Memory barriers come in four basic varieties:
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(1) Write (or store) memory barriers.
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A write memory barrier gives a guarantee that all the STORE operations
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specified before the barrier will appear to happen before all the STORE
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operations specified after the barrier with respect to the other
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components of the system.
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A write barrier is a partial ordering on stores only; it is not required
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to have any effect on loads.
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A CPU can be viewed as committing a sequence of store operations to the
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memory system as time progresses. All stores before a write barrier will
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occur in the sequence _before_ all the stores after the write barrier.
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[!] Note that write barriers should normally be paired with read or data
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dependency barriers; see the "SMP barrier pairing" subsection.
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(2) Data dependency barriers.
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A data dependency barrier is a weaker form of read barrier. In the case
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where two loads are performed such that the second depends on the result
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of the first (eg: the first load retrieves the address to which the second
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load will be directed), a data dependency barrier would be required to
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make sure that the target of the second load is updated before the address
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obtained by the first load is accessed.
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A data dependency barrier is a partial ordering on interdependent loads
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only; it is not required to have any effect on stores, independent loads
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or overlapping loads.
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As mentioned in (1), the other CPUs in the system can be viewed as
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committing sequences of stores to the memory system that the CPU being
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considered can then perceive. A data dependency barrier issued by the CPU
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under consideration guarantees that for any load preceding it, if that
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load touches one of a sequence of stores from another CPU, then by the
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time the barrier completes, the effects of all the stores prior to that
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touched by the load will be perceptible to any loads issued after the data
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dependency barrier.
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See the "Examples of memory barrier sequences" subsection for diagrams
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showing the ordering constraints.
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[!] Note that the first load really has to have a _data_ dependency and
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not a control dependency. If the address for the second load is dependent
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on the first load, but the dependency is through a conditional rather than
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actually loading the address itself, then it's a _control_ dependency and
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a full read barrier or better is required. See the "Control dependencies"
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subsection for more information.
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[!] Note that data dependency barriers should normally be paired with
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write barriers; see the "SMP barrier pairing" subsection.
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(3) Read (or load) memory barriers.
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A read barrier is a data dependency barrier plus a guarantee that all the
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LOAD operations specified before the barrier will appear to happen before
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all the LOAD operations specified after the barrier with respect to the
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other components of the system.
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A read barrier is a partial ordering on loads only; it is not required to
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have any effect on stores.
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Read memory barriers imply data dependency barriers, and so can substitute
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for them.
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[!] Note that read barriers should normally be paired with write barriers;
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see the "SMP barrier pairing" subsection.
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(4) General memory barriers.
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A general memory barrier gives a guarantee that all the LOAD and STORE
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operations specified before the barrier will appear to happen before all
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the LOAD and STORE operations specified after the barrier with respect to
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the other components of the system.
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A general memory barrier is a partial ordering over both loads and stores.
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General memory barriers imply both read and write memory barriers, and so
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can substitute for either.
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And a couple of implicit varieties:
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(5) LOCK operations.
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This acts as a one-way permeable barrier. It guarantees that all memory
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operations after the LOCK operation will appear to happen after the LOCK
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operation with respect to the other components of the system.
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Memory operations that occur before a LOCK operation may appear to happen
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after it completes.
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A LOCK operation should almost always be paired with an UNLOCK operation.
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(6) UNLOCK operations.
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This also acts as a one-way permeable barrier. It guarantees that all
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memory operations before the UNLOCK operation will appear to happen before
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the UNLOCK operation with respect to the other components of the system.
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Memory operations that occur after an UNLOCK operation may appear to
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happen before it completes.
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LOCK and UNLOCK operations are guaranteed to appear with respect to each
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other strictly in the order specified.
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The use of LOCK and UNLOCK operations generally precludes the need for
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other sorts of memory barrier (but note the exceptions mentioned in the
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subsection "MMIO write barrier").
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Memory barriers are only required where there's a possibility of interaction
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between two CPUs or between a CPU and a device. If it can be guaranteed that
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there won't be any such interaction in any particular piece of code, then
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memory barriers are unnecessary in that piece of code.
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Note that these are the _minimum_ guarantees. Different architectures may give
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more substantial guarantees, but they may _not_ be relied upon outside of arch
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specific code.
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WHAT MAY NOT BE ASSUMED ABOUT MEMORY BARRIERS?
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----------------------------------------------
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There are certain things that the Linux kernel memory barriers do not guarantee:
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(*) There is no guarantee that any of the memory accesses specified before a
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memory barrier will be _complete_ by the completion of a memory barrier
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instruction; the barrier can be considered to draw a line in that CPU's
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access queue that accesses of the appropriate type may not cross.
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(*) There is no guarantee that issuing a memory barrier on one CPU will have
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any direct effect on another CPU or any other hardware in the system. The
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indirect effect will be the order in which the second CPU sees the effects
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of the first CPU's accesses occur, but see the next point:
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(*) There is no guarantee that a CPU will see the correct order of effects
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from a second CPU's accesses, even _if_ the second CPU uses a memory
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barrier, unless the first CPU _also_ uses a matching memory barrier (see
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the subsection on "SMP Barrier Pairing").
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(*) There is no guarantee that some intervening piece of off-the-CPU
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hardware[*] will not reorder the memory accesses. CPU cache coherency
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mechanisms should propagate the indirect effects of a memory barrier
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between CPUs, but might not do so in order.
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[*] For information on bus mastering DMA and coherency please read:
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Documentation/pci.txt
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Documentation/DMA-mapping.txt
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Documentation/DMA-API.txt
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DATA DEPENDENCY BARRIERS
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------------------------
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The usage requirements of data dependency barriers are a little subtle, and
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it's not always obvious that they're needed. To illustrate, consider the
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following sequence of events:
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CPU 1 CPU 2
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=============== ===============
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{ A == 1, B == 2, C = 3, P == &A, Q == &C }
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B = 4;
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<write barrier>
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P = &B
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Q = P;
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D = *Q;
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There's a clear data dependency here, and it would seem that by the end of the
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sequence, Q must be either &A or &B, and that:
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(Q == &A) implies (D == 1)
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(Q == &B) implies (D == 4)
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But! CPU 2's perception of P may be updated _before_ its perception of B, thus
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leading to the following situation:
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(Q == &B) and (D == 2) ????
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Whilst this may seem like a failure of coherency or causality maintenance, it
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isn't, and this behaviour can be observed on certain real CPUs (such as the DEC
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Alpha).
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To deal with this, a data dependency barrier or better must be inserted
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between the address load and the data load:
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CPU 1 CPU 2
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=============== ===============
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{ A == 1, B == 2, C = 3, P == &A, Q == &C }
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B = 4;
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<write barrier>
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P = &B
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Q = P;
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<data dependency barrier>
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D = *Q;
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This enforces the occurrence of one of the two implications, and prevents the
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third possibility from arising.
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[!] Note that this extremely counterintuitive situation arises most easily on
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machines with split caches, so that, for example, one cache bank processes
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even-numbered cache lines and the other bank processes odd-numbered cache
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lines. The pointer P might be stored in an odd-numbered cache line, and the
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variable B might be stored in an even-numbered cache line. Then, if the
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even-numbered bank of the reading CPU's cache is extremely busy while the
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odd-numbered bank is idle, one can see the new value of the pointer P (&B),
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but the old value of the variable B (2).
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Another example of where data dependency barriers might by required is where a
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number is read from memory and then used to calculate the index for an array
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access:
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CPU 1 CPU 2
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=============== ===============
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{ M[0] == 1, M[1] == 2, M[3] = 3, P == 0, Q == 3 }
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M[1] = 4;
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<write barrier>
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P = 1
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Q = P;
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<data dependency barrier>
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D = M[Q];
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The data dependency barrier is very important to the RCU system, for example.
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See rcu_dereference() in include/linux/rcupdate.h. This permits the current
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target of an RCU'd pointer to be replaced with a new modified target, without
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the replacement target appearing to be incompletely initialised.
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See also the subsection on "Cache Coherency" for a more thorough example.
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CONTROL DEPENDENCIES
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--------------------
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A control dependency requires a full read memory barrier, not simply a data
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dependency barrier to make it work correctly. Consider the following bit of
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code:
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q = &a;
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if (p)
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q = &b;
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<data dependency barrier>
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x = *q;
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This will not have the desired effect because there is no actual data
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dependency, but rather a control dependency that the CPU may short-circuit by
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attempting to predict the outcome in advance. In such a case what's actually
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required is:
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q = &a;
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if (p)
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q = &b;
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<read barrier>
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x = *q;
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SMP BARRIER PAIRING
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-------------------
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When dealing with CPU-CPU interactions, certain types of memory barrier should
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always be paired. A lack of appropriate pairing is almost certainly an error.
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A write barrier should always be paired with a data dependency barrier or read
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barrier, though a general barrier would also be viable. Similarly a read
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barrier or a data dependency barrier should always be paired with at least an
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write barrier, though, again, a general barrier is viable:
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CPU 1 CPU 2
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=============== ===============
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a = 1;
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<write barrier>
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b = 2; x = b;
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<read barrier>
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y = a;
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Or:
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CPU 1 CPU 2
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=============== ===============================
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a = 1;
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<write barrier>
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b = &a; x = b;
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<data dependency barrier>
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y = *x;
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Basically, the read barrier always has to be there, even though it can be of
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the "weaker" type.
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[!] Note that the stores before the write barrier would normally be expected to
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match the loads after the read barrier or the data dependency barrier, and vice
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versa:
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CPU 1 CPU 2
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=============== ===============
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a = 1; }---- --->{ v = c
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b = 2; } \ / { w = d
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<write barrier> \ <read barrier>
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c = 3; } / \ { x = a;
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d = 4; }---- --->{ y = b;
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EXAMPLES OF MEMORY BARRIER SEQUENCES
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------------------------------------
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Firstly, write barriers act as partial orderings on store operations.
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Consider the following sequence of events:
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CPU 1
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=======================
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STORE A = 1
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STORE B = 2
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STORE C = 3
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<write barrier>
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STORE D = 4
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STORE E = 5
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This sequence of events is committed to the memory coherence system in an order
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that the rest of the system might perceive as the unordered set of { STORE A,
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STORE B, STORE C } all occurring before the unordered set of { STORE D, STORE E
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}:
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+-------+ : :
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| | +------+
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| |------>| C=3 | } /\
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| | : +------+ }----- \ -----> Events perceptible to
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| | : | A=1 | } \/ the rest of the system
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| | : +------+ }
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| CPU 1 | : | B=2 | }
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| | +------+ }
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| | wwwwwwwwwwwwwwww } <--- At this point the write barrier
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| | +------+ } requires all stores prior to the
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| | : | E=5 | } barrier to be committed before
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| | : +------+ } further stores may take place
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| |------>| D=4 | }
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| | +------+
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+-------+ : :
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| Sequence in which stores are committed to the
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| memory system by CPU 1
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V
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Secondly, data dependency barriers act as partial orderings on data-dependent
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loads. Consider the following sequence of events:
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CPU 1 CPU 2
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======================= =======================
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{ B = 7; X = 9; Y = 8; C = &Y }
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STORE A = 1
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STORE B = 2
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<write barrier>
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STORE C = &B LOAD X
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STORE D = 4 LOAD C (gets &B)
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LOAD *C (reads B)
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Without intervention, CPU 2 may perceive the events on CPU 1 in some
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effectively random order, despite the write barrier issued by CPU 1:
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+-------+ : : : :
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| | +------+ +-------+ | Sequence of update
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| |------>| B=2 |----- --->| Y->8 | | of perception on
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| | : +------+ \ +-------+ | CPU 2
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| CPU 1 | : | A=1 | \ --->| C->&Y | V
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| | +------+ | +-------+
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| | wwwwwwwwwwwwwwww | : :
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| | +------+ | : :
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| | : | C=&B |--- | : : +-------+
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| | : +------+ \ | +-------+ | |
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| |------>| D=4 | ----------->| C->&B |------>| |
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| | +------+ | +-------+ | |
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+-------+ : : | : : | |
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| : : | |
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| : : | CPU 2 |
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| +-------+ | |
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Apparently incorrect ---> | | B->7 |------>| |
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perception of B (!) | +-------+ | |
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| : : | |
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| +-------+ | |
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The load of X holds ---> \ | X->9 |------>| |
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up the maintenance \ +-------+ | |
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of coherence of B ----->| B->2 | +-------+
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+-------+
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: :
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In the above example, CPU 2 perceives that B is 7, despite the load of *C
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(which would be B) coming after the LOAD of C.
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If, however, a data dependency barrier were to be placed between the load of C
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and the load of *C (ie: B) on CPU 2:
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CPU 1 CPU 2
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======================= =======================
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{ B = 7; X = 9; Y = 8; C = &Y }
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STORE A = 1
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STORE B = 2
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<write barrier>
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STORE C = &B LOAD X
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STORE D = 4 LOAD C (gets &B)
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<data dependency barrier>
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LOAD *C (reads B)
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then the following will occur:
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+-------+ : : : :
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| | +------+ +-------+
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| |------>| B=2 |----- --->| Y->8 |
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| | : +------+ \ +-------+
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| CPU 1 | : | A=1 | \ --->| C->&Y |
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| | +------+ | +-------+
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| | wwwwwwwwwwwwwwww | : :
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| | +------+ | : :
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| | : | C=&B |--- | : : +-------+
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| | : +------+ \ | +-------+ | |
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| |------>| D=4 | ----------->| C->&B |------>| |
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| | +------+ | +-------+ | |
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+-------+ : : | : : | |
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| : : | |
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| : : | CPU 2 |
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| +-------+ | |
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| | X->9 |------>| |
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| +-------+ | |
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Makes sure all effects ---> \ ddddddddddddddddd | |
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prior to the store of C \ +-------+ | |
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are perceptible to ----->| B->2 |------>| |
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subsequent loads +-------+ | |
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: : +-------+
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And thirdly, a read barrier acts as a partial order on loads. Consider the
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following sequence of events:
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CPU 1 CPU 2
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======================= =======================
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{ A = 0, B = 9 }
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STORE A=1
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<write barrier>
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STORE B=2
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LOAD B
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LOAD A
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Without intervention, CPU 2 may then choose to perceive the events on CPU 1 in
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some effectively random order, despite the write barrier issued by CPU 1:
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+-------+ : : : :
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| | +------+ +-------+
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| |------>| A=1 |------ --->| A->0 |
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| | +------+ \ +-------+
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| CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
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| | +------+ | +-------+
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| |------>| B=2 |--- | : :
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| | +------+ \ | : : +-------+
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+-------+ : : \ | +-------+ | |
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---------->| B->2 |------>| |
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| +-------+ | CPU 2 |
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| | A->0 |------>| |
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| +-------+ | |
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| : : +-------+
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\ : :
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\ +-------+
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---->| A->1 |
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+-------+
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: :
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If, however, a read barrier were to be placed between the load of B and the
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load of A on CPU 2:
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CPU 1 CPU 2
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======================= =======================
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{ A = 0, B = 9 }
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STORE A=1
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<write barrier>
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STORE B=2
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LOAD B
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<read barrier>
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LOAD A
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then the partial ordering imposed by CPU 1 will be perceived correctly by CPU
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2:
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+-------+ : : : :
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| | +------+ +-------+
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| |------>| A=1 |------ --->| A->0 |
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| | +------+ \ +-------+
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| CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
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| | +------+ | +-------+
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| |------>| B=2 |--- | : :
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| | +------+ \ | : : +-------+
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+-------+ : : \ | +-------+ | |
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---------->| B->2 |------>| |
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| +-------+ | CPU 2 |
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| : : | |
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| : : | |
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At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
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barrier causes all effects \ +-------+ | |
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prior to the storage of B ---->| A->1 |------>| |
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to be perceptible to CPU 2 +-------+ | |
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: : +-------+
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To illustrate this more completely, consider what could happen if the code
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contained a load of A either side of the read barrier:
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CPU 1 CPU 2
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======================= =======================
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{ A = 0, B = 9 }
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STORE A=1
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<write barrier>
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STORE B=2
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LOAD B
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LOAD A [first load of A]
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<read barrier>
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LOAD A [second load of A]
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Even though the two loads of A both occur after the load of B, they may both
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come up with different values:
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+-------+ : : : :
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| | +------+ +-------+
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| |------>| A=1 |------ --->| A->0 |
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| | +------+ \ +-------+
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| CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
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| | +------+ | +-------+
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| |------>| B=2 |--- | : :
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| | +------+ \ | : : +-------+
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+-------+ : : \ | +-------+ | |
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---------->| B->2 |------>| |
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| +-------+ | CPU 2 |
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| : : | |
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| : : | |
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| +-------+ | |
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| | A->0 |------>| 1st |
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| +-------+ | |
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At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
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barrier causes all effects \ +-------+ | |
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prior to the storage of B ---->| A->1 |------>| 2nd |
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to be perceptible to CPU 2 +-------+ | |
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: : +-------+
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But it may be that the update to A from CPU 1 becomes perceptible to CPU 2
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before the read barrier completes anyway:
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+-------+ : : : :
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| | +------+ +-------+
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| |------>| A=1 |------ --->| A->0 |
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| | +------+ \ +-------+
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| CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
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| | +------+ | +-------+
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| |------>| B=2 |--- | : :
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| | +------+ \ | : : +-------+
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+-------+ : : \ | +-------+ | |
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---------->| B->2 |------>| |
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| +-------+ | CPU 2 |
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| : : | |
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\ : : | |
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\ +-------+ | |
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---->| A->1 |------>| 1st |
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+-------+ | |
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rrrrrrrrrrrrrrrrr | |
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+-------+ | |
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| A->1 |------>| 2nd |
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+-------+ | |
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: : +-------+
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The guarantee is that the second load will always come up with A == 1 if the
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load of B came up with B == 2. No such guarantee exists for the first load of
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A; that may come up with either A == 0 or A == 1.
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READ MEMORY BARRIERS VS LOAD SPECULATION
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----------------------------------------
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Many CPUs speculate with loads: that is they see that they will need to load an
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item from memory, and they find a time where they're not using the bus for any
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other loads, and so do the load in advance - even though they haven't actually
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got to that point in the instruction execution flow yet. This permits the
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actual load instruction to potentially complete immediately because the CPU
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already has the value to hand.
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It may turn out that the CPU didn't actually need the value - perhaps because a
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branch circumvented the load - in which case it can discard the value or just
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cache it for later use.
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Consider:
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CPU 1 CPU 2
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======================= =======================
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LOAD B
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DIVIDE } Divide instructions generally
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DIVIDE } take a long time to perform
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LOAD A
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Which might appear as this:
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: : +-------+
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+-------+ | |
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--->| B->2 |------>| |
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+-------+ | CPU 2 |
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: :DIVIDE | |
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+-------+ | |
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The CPU being busy doing a ---> --->| A->0 |~~~~ | |
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division speculates on the +-------+ ~ | |
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LOAD of A : : ~ | |
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: :DIVIDE | |
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: : ~ | |
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Once the divisions are complete --> : : ~-->| |
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the CPU can then perform the : : | |
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LOAD with immediate effect : : +-------+
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Placing a read barrier or a data dependency barrier just before the second
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load:
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CPU 1 CPU 2
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======================= =======================
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LOAD B
|
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DIVIDE
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DIVIDE
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<read barrier>
|
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LOAD A
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will force any value speculatively obtained to be reconsidered to an extent
|
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dependent on the type of barrier used. If there was no change made to the
|
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speculated memory location, then the speculated value will just be used:
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: : +-------+
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+-------+ | |
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--->| B->2 |------>| |
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+-------+ | CPU 2 |
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: :DIVIDE | |
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+-------+ | |
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The CPU being busy doing a ---> --->| A->0 |~~~~ | |
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division speculates on the +-------+ ~ | |
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LOAD of A : : ~ | |
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: :DIVIDE | |
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: : ~ | |
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: : ~ | |
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rrrrrrrrrrrrrrrr~ | |
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: : ~ | |
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: : ~-->| |
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: : | |
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: : +-------+
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but if there was an update or an invalidation from another CPU pending, then
|
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the speculation will be cancelled and the value reloaded:
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|
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: : +-------+
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+-------+ | |
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--->| B->2 |------>| |
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+-------+ | CPU 2 |
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: :DIVIDE | |
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+-------+ | |
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The CPU being busy doing a ---> --->| A->0 |~~~~ | |
|
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division speculates on the +-------+ ~ | |
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LOAD of A : : ~ | |
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: :DIVIDE | |
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: : ~ | |
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: : ~ | |
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rrrrrrrrrrrrrrrrr | |
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+-------+ | |
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The speculation is discarded ---> --->| A->1 |------>| |
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and an updated value is +-------+ | |
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retrieved : : +-------+
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========================
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EXPLICIT KERNEL BARRIERS
|
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========================
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The Linux kernel has a variety of different barriers that act at different
|
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levels:
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(*) Compiler barrier.
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(*) CPU memory barriers.
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(*) MMIO write barrier.
|
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COMPILER BARRIER
|
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----------------
|
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|
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The Linux kernel has an explicit compiler barrier function that prevents the
|
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compiler from moving the memory accesses either side of it to the other side:
|
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|
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barrier();
|
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|
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This is a general barrier - lesser varieties of compiler barrier do not exist.
|
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|
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The compiler barrier has no direct effect on the CPU, which may then reorder
|
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things however it wishes.
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CPU MEMORY BARRIERS
|
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-------------------
|
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|
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The Linux kernel has eight basic CPU memory barriers:
|
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|
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TYPE MANDATORY SMP CONDITIONAL
|
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=============== ======================= ===========================
|
|
GENERAL mb() smp_mb()
|
|
WRITE wmb() smp_wmb()
|
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READ rmb() smp_rmb()
|
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DATA DEPENDENCY read_barrier_depends() smp_read_barrier_depends()
|
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|
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|
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All CPU memory barriers unconditionally imply compiler barriers.
|
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|
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SMP memory barriers are reduced to compiler barriers on uniprocessor compiled
|
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systems because it is assumed that a CPU will appear to be self-consistent,
|
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and will order overlapping accesses correctly with respect to itself.
|
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|
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[!] Note that SMP memory barriers _must_ be used to control the ordering of
|
|
references to shared memory on SMP systems, though the use of locking instead
|
|
is sufficient.
|
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|
|
Mandatory barriers should not be used to control SMP effects, since mandatory
|
|
barriers unnecessarily impose overhead on UP systems. They may, however, be
|
|
used to control MMIO effects on accesses through relaxed memory I/O windows.
|
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These are required even on non-SMP systems as they affect the order in which
|
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memory operations appear to a device by prohibiting both the compiler and the
|
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CPU from reordering them.
|
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|
|
|
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There are some more advanced barrier functions:
|
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|
|
(*) set_mb(var, value)
|
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|
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This assigns the value to the variable and then inserts a full memory
|
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barrier after it, depending on the function. It isn't guaranteed to
|
|
insert anything more than a compiler barrier in a UP compilation.
|
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|
|
|
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(*) smp_mb__before_atomic_dec();
|
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(*) smp_mb__after_atomic_dec();
|
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(*) smp_mb__before_atomic_inc();
|
|
(*) smp_mb__after_atomic_inc();
|
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|
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These are for use with atomic add, subtract, increment and decrement
|
|
functions that don't return a value, especially when used for reference
|
|
counting. These functions do not imply memory barriers.
|
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|
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As an example, consider a piece of code that marks an object as being dead
|
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and then decrements the object's reference count:
|
|
|
|
obj->dead = 1;
|
|
smp_mb__before_atomic_dec();
|
|
atomic_dec(&obj->ref_count);
|
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|
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This makes sure that the death mark on the object is perceived to be set
|
|
*before* the reference counter is decremented.
|
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|
|
See Documentation/atomic_ops.txt for more information. See the "Atomic
|
|
operations" subsection for information on where to use these.
|
|
|
|
|
|
(*) smp_mb__before_clear_bit(void);
|
|
(*) smp_mb__after_clear_bit(void);
|
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|
|
These are for use similar to the atomic inc/dec barriers. These are
|
|
typically used for bitwise unlocking operations, so care must be taken as
|
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there are no implicit memory barriers here either.
|
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|
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Consider implementing an unlock operation of some nature by clearing a
|
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locking bit. The clear_bit() would then need to be barriered like this:
|
|
|
|
smp_mb__before_clear_bit();
|
|
clear_bit( ... );
|
|
|
|
This prevents memory operations before the clear leaking to after it. See
|
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the subsection on "Locking Functions" with reference to UNLOCK operation
|
|
implications.
|
|
|
|
See Documentation/atomic_ops.txt for more information. See the "Atomic
|
|
operations" subsection for information on where to use these.
|
|
|
|
|
|
MMIO WRITE BARRIER
|
|
------------------
|
|
|
|
The Linux kernel also has a special barrier for use with memory-mapped I/O
|
|
writes:
|
|
|
|
mmiowb();
|
|
|
|
This is a variation on the mandatory write barrier that causes writes to weakly
|
|
ordered I/O regions to be partially ordered. Its effects may go beyond the
|
|
CPU->Hardware interface and actually affect the hardware at some level.
|
|
|
|
See the subsection "Locks vs I/O accesses" for more information.
|
|
|
|
|
|
===============================
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IMPLICIT KERNEL MEMORY BARRIERS
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===============================
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Some of the other functions in the linux kernel imply memory barriers, amongst
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which are locking and scheduling functions.
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This specification is a _minimum_ guarantee; any particular architecture may
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provide more substantial guarantees, but these may not be relied upon outside
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of arch specific code.
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LOCKING FUNCTIONS
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-----------------
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The Linux kernel has a number of locking constructs:
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(*) spin locks
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(*) R/W spin locks
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(*) mutexes
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(*) semaphores
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(*) R/W semaphores
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(*) RCU
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In all cases there are variants on "LOCK" operations and "UNLOCK" operations
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for each construct. These operations all imply certain barriers:
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(1) LOCK operation implication:
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Memory operations issued after the LOCK will be completed after the LOCK
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operation has completed.
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Memory operations issued before the LOCK may be completed after the LOCK
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operation has completed.
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(2) UNLOCK operation implication:
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Memory operations issued before the UNLOCK will be completed before the
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UNLOCK operation has completed.
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Memory operations issued after the UNLOCK may be completed before the
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UNLOCK operation has completed.
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(3) LOCK vs LOCK implication:
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All LOCK operations issued before another LOCK operation will be completed
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before that LOCK operation.
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(4) LOCK vs UNLOCK implication:
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All LOCK operations issued before an UNLOCK operation will be completed
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before the UNLOCK operation.
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All UNLOCK operations issued before a LOCK operation will be completed
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before the LOCK operation.
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(5) Failed conditional LOCK implication:
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Certain variants of the LOCK operation may fail, either due to being
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unable to get the lock immediately, or due to receiving an unblocked
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signal whilst asleep waiting for the lock to become available. Failed
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locks do not imply any sort of barrier.
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Therefore, from (1), (2) and (4) an UNLOCK followed by an unconditional LOCK is
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equivalent to a full barrier, but a LOCK followed by an UNLOCK is not.
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[!] Note: one of the consequences of LOCKs and UNLOCKs being only one-way
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barriers is that the effects of instructions outside of a critical section
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may seep into the inside of the critical section.
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A LOCK followed by an UNLOCK may not be assumed to be full memory barrier
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because it is possible for an access preceding the LOCK to happen after the
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LOCK, and an access following the UNLOCK to happen before the UNLOCK, and the
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two accesses can themselves then cross:
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*A = a;
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LOCK
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UNLOCK
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*B = b;
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may occur as:
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LOCK, STORE *B, STORE *A, UNLOCK
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Locks and semaphores may not provide any guarantee of ordering on UP compiled
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systems, and so cannot be counted on in such a situation to actually achieve
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anything at all - especially with respect to I/O accesses - unless combined
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with interrupt disabling operations.
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See also the section on "Inter-CPU locking barrier effects".
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As an example, consider the following:
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*A = a;
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*B = b;
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LOCK
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*C = c;
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*D = d;
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UNLOCK
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*E = e;
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*F = f;
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The following sequence of events is acceptable:
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LOCK, {*F,*A}, *E, {*C,*D}, *B, UNLOCK
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[+] Note that {*F,*A} indicates a combined access.
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But none of the following are:
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{*F,*A}, *B, LOCK, *C, *D, UNLOCK, *E
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*A, *B, *C, LOCK, *D, UNLOCK, *E, *F
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*A, *B, LOCK, *C, UNLOCK, *D, *E, *F
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*B, LOCK, *C, *D, UNLOCK, {*F,*A}, *E
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INTERRUPT DISABLING FUNCTIONS
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-----------------------------
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Functions that disable interrupts (LOCK equivalent) and enable interrupts
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(UNLOCK equivalent) will act as compiler barriers only. So if memory or I/O
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barriers are required in such a situation, they must be provided from some
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other means.
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MISCELLANEOUS FUNCTIONS
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-----------------------
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Other functions that imply barriers:
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(*) schedule() and similar imply full memory barriers.
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=================================
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INTER-CPU LOCKING BARRIER EFFECTS
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=================================
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On SMP systems locking primitives give a more substantial form of barrier: one
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that does affect memory access ordering on other CPUs, within the context of
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conflict on any particular lock.
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LOCKS VS MEMORY ACCESSES
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------------------------
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Consider the following: the system has a pair of spinlocks (M) and (Q), and
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three CPUs; then should the following sequence of events occur:
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CPU 1 CPU 2
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=============================== ===============================
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*A = a; *E = e;
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LOCK M LOCK Q
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*B = b; *F = f;
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*C = c; *G = g;
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UNLOCK M UNLOCK Q
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*D = d; *H = h;
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Then there is no guarantee as to what order CPU 3 will see the accesses to *A
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through *H occur in, other than the constraints imposed by the separate locks
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on the separate CPUs. It might, for example, see:
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*E, LOCK M, LOCK Q, *G, *C, *F, *A, *B, UNLOCK Q, *D, *H, UNLOCK M
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But it won't see any of:
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*B, *C or *D preceding LOCK M
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*A, *B or *C following UNLOCK M
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*F, *G or *H preceding LOCK Q
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*E, *F or *G following UNLOCK Q
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However, if the following occurs:
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CPU 1 CPU 2
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=============================== ===============================
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*A = a;
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LOCK M [1]
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*B = b;
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*C = c;
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UNLOCK M [1]
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*D = d; *E = e;
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LOCK M [2]
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*F = f;
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*G = g;
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UNLOCK M [2]
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*H = h;
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CPU 3 might see:
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*E, LOCK M [1], *C, *B, *A, UNLOCK M [1],
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LOCK M [2], *H, *F, *G, UNLOCK M [2], *D
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But assuming CPU 1 gets the lock first, CPU 3 won't see any of:
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*B, *C, *D, *F, *G or *H preceding LOCK M [1]
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*A, *B or *C following UNLOCK M [1]
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*F, *G or *H preceding LOCK M [2]
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*A, *B, *C, *E, *F or *G following UNLOCK M [2]
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LOCKS VS I/O ACCESSES
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---------------------
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Under certain circumstances (especially involving NUMA), I/O accesses within
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two spinlocked sections on two different CPUs may be seen as interleaved by the
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PCI bridge, because the PCI bridge does not necessarily participate in the
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cache-coherence protocol, and is therefore incapable of issuing the required
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read memory barriers.
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For example:
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CPU 1 CPU 2
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=============================== ===============================
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spin_lock(Q)
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writel(0, ADDR)
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writel(1, DATA);
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spin_unlock(Q);
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spin_lock(Q);
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writel(4, ADDR);
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writel(5, DATA);
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spin_unlock(Q);
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may be seen by the PCI bridge as follows:
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STORE *ADDR = 0, STORE *ADDR = 4, STORE *DATA = 1, STORE *DATA = 5
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which would probably cause the hardware to malfunction.
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What is necessary here is to intervene with an mmiowb() before dropping the
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spinlock, for example:
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CPU 1 CPU 2
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=============================== ===============================
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spin_lock(Q)
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writel(0, ADDR)
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writel(1, DATA);
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mmiowb();
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spin_unlock(Q);
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spin_lock(Q);
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writel(4, ADDR);
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writel(5, DATA);
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mmiowb();
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spin_unlock(Q);
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this will ensure that the two stores issued on CPU 1 appear at the PCI bridge
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before either of the stores issued on CPU 2.
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Furthermore, following a store by a load from the same device obviates the need
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for the mmiowb(), because the load forces the store to complete before the load
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is performed:
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CPU 1 CPU 2
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=============================== ===============================
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spin_lock(Q)
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writel(0, ADDR)
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a = readl(DATA);
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spin_unlock(Q);
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spin_lock(Q);
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writel(4, ADDR);
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b = readl(DATA);
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spin_unlock(Q);
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See Documentation/DocBook/deviceiobook.tmpl for more information.
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=================================
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WHERE ARE MEMORY BARRIERS NEEDED?
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=================================
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Under normal operation, memory operation reordering is generally not going to
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be a problem as a single-threaded linear piece of code will still appear to
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work correctly, even if it's in an SMP kernel. There are, however, three
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circumstances in which reordering definitely _could_ be a problem:
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(*) Interprocessor interaction.
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(*) Atomic operations.
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(*) Accessing devices.
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(*) Interrupts.
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INTERPROCESSOR INTERACTION
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--------------------------
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When there's a system with more than one processor, more than one CPU in the
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system may be working on the same data set at the same time. This can cause
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synchronisation problems, and the usual way of dealing with them is to use
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locks. Locks, however, are quite expensive, and so it may be preferable to
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operate without the use of a lock if at all possible. In such a case
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operations that affect both CPUs may have to be carefully ordered to prevent
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a malfunction.
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Consider, for example, the R/W semaphore slow path. Here a waiting process is
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queued on the semaphore, by virtue of it having a piece of its stack linked to
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the semaphore's list of waiting processes:
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struct rw_semaphore {
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...
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spinlock_t lock;
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struct list_head waiters;
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};
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struct rwsem_waiter {
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struct list_head list;
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struct task_struct *task;
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};
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To wake up a particular waiter, the up_read() or up_write() functions have to:
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(1) read the next pointer from this waiter's record to know as to where the
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next waiter record is;
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(2) read the pointer to the waiter's task structure;
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(3) clear the task pointer to tell the waiter it has been given the semaphore;
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(4) call wake_up_process() on the task; and
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(5) release the reference held on the waiter's task struct.
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In other words, it has to perform this sequence of events:
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LOAD waiter->list.next;
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LOAD waiter->task;
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STORE waiter->task;
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CALL wakeup
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RELEASE task
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and if any of these steps occur out of order, then the whole thing may
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malfunction.
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Once it has queued itself and dropped the semaphore lock, the waiter does not
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get the lock again; it instead just waits for its task pointer to be cleared
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before proceeding. Since the record is on the waiter's stack, this means that
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if the task pointer is cleared _before_ the next pointer in the list is read,
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another CPU might start processing the waiter and might clobber the waiter's
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stack before the up*() function has a chance to read the next pointer.
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Consider then what might happen to the above sequence of events:
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CPU 1 CPU 2
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=============================== ===============================
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down_xxx()
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Queue waiter
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Sleep
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up_yyy()
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LOAD waiter->task;
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STORE waiter->task;
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Woken up by other event
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<preempt>
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Resume processing
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down_xxx() returns
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call foo()
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foo() clobbers *waiter
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</preempt>
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LOAD waiter->list.next;
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--- OOPS ---
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This could be dealt with using the semaphore lock, but then the down_xxx()
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function has to needlessly get the spinlock again after being woken up.
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The way to deal with this is to insert a general SMP memory barrier:
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LOAD waiter->list.next;
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LOAD waiter->task;
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smp_mb();
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STORE waiter->task;
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CALL wakeup
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RELEASE task
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In this case, the barrier makes a guarantee that all memory accesses before the
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barrier will appear to happen before all the memory accesses after the barrier
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with respect to the other CPUs on the system. It does _not_ guarantee that all
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the memory accesses before the barrier will be complete by the time the barrier
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instruction itself is complete.
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On a UP system - where this wouldn't be a problem - the smp_mb() is just a
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compiler barrier, thus making sure the compiler emits the instructions in the
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right order without actually intervening in the CPU. Since there's only one
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CPU, that CPU's dependency ordering logic will take care of everything else.
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ATOMIC OPERATIONS
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-----------------
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Whilst they are technically interprocessor interaction considerations, atomic
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operations are noted specially as some of them imply full memory barriers and
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some don't, but they're very heavily relied on as a group throughout the
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kernel.
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Any atomic operation that modifies some state in memory and returns information
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about the state (old or new) implies an SMP-conditional general memory barrier
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(smp_mb()) on each side of the actual operation. These include:
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xchg();
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cmpxchg();
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atomic_cmpxchg();
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atomic_inc_return();
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atomic_dec_return();
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atomic_add_return();
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atomic_sub_return();
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atomic_inc_and_test();
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atomic_dec_and_test();
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atomic_sub_and_test();
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atomic_add_negative();
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atomic_add_unless();
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test_and_set_bit();
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test_and_clear_bit();
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test_and_change_bit();
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These are used for such things as implementing LOCK-class and UNLOCK-class
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operations and adjusting reference counters towards object destruction, and as
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such the implicit memory barrier effects are necessary.
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The following operations are potential problems as they do _not_ imply memory
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barriers, but might be used for implementing such things as UNLOCK-class
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operations:
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atomic_set();
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set_bit();
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clear_bit();
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change_bit();
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With these the appropriate explicit memory barrier should be used if necessary
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(smp_mb__before_clear_bit() for instance).
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The following also do _not_ imply memory barriers, and so may require explicit
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memory barriers under some circumstances (smp_mb__before_atomic_dec() for
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instance):
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atomic_add();
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atomic_sub();
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atomic_inc();
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atomic_dec();
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If they're used for statistics generation, then they probably don't need memory
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barriers, unless there's a coupling between statistical data.
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If they're used for reference counting on an object to control its lifetime,
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they probably don't need memory barriers because either the reference count
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will be adjusted inside a locked section, or the caller will already hold
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sufficient references to make the lock, and thus a memory barrier unnecessary.
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If they're used for constructing a lock of some description, then they probably
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do need memory barriers as a lock primitive generally has to do things in a
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specific order.
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Basically, each usage case has to be carefully considered as to whether memory
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barriers are needed or not.
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[!] Note that special memory barrier primitives are available for these
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situations because on some CPUs the atomic instructions used imply full memory
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barriers, and so barrier instructions are superfluous in conjunction with them,
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and in such cases the special barrier primitives will be no-ops.
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See Documentation/atomic_ops.txt for more information.
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ACCESSING DEVICES
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-----------------
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Many devices can be memory mapped, and so appear to the CPU as if they're just
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a set of memory locations. To control such a device, the driver usually has to
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make the right memory accesses in exactly the right order.
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However, having a clever CPU or a clever compiler creates a potential problem
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in that the carefully sequenced accesses in the driver code won't reach the
|
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device in the requisite order if the CPU or the compiler thinks it is more
|
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efficient to reorder, combine or merge accesses - something that would cause
|
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the device to malfunction.
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Inside of the Linux kernel, I/O should be done through the appropriate accessor
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routines - such as inb() or writel() - which know how to make such accesses
|
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appropriately sequential. Whilst this, for the most part, renders the explicit
|
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use of memory barriers unnecessary, there are a couple of situations where they
|
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might be needed:
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(1) On some systems, I/O stores are not strongly ordered across all CPUs, and
|
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so for _all_ general drivers locks should be used and mmiowb() must be
|
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issued prior to unlocking the critical section.
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(2) If the accessor functions are used to refer to an I/O memory window with
|
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relaxed memory access properties, then _mandatory_ memory barriers are
|
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required to enforce ordering.
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See Documentation/DocBook/deviceiobook.tmpl for more information.
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INTERRUPTS
|
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----------
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A driver may be interrupted by its own interrupt service routine, and thus the
|
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two parts of the driver may interfere with each other's attempts to control or
|
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access the device.
|
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This may be alleviated - at least in part - by disabling local interrupts (a
|
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form of locking), such that the critical operations are all contained within
|
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the interrupt-disabled section in the driver. Whilst the driver's interrupt
|
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routine is executing, the driver's core may not run on the same CPU, and its
|
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interrupt is not permitted to happen again until the current interrupt has been
|
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handled, thus the interrupt handler does not need to lock against that.
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However, consider a driver that was talking to an ethernet card that sports an
|
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address register and a data register. If that driver's core talks to the card
|
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under interrupt-disablement and then the driver's interrupt handler is invoked:
|
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|
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LOCAL IRQ DISABLE
|
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writew(ADDR, 3);
|
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writew(DATA, y);
|
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LOCAL IRQ ENABLE
|
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<interrupt>
|
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writew(ADDR, 4);
|
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q = readw(DATA);
|
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</interrupt>
|
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The store to the data register might happen after the second store to the
|
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address register if ordering rules are sufficiently relaxed:
|
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STORE *ADDR = 3, STORE *ADDR = 4, STORE *DATA = y, q = LOAD *DATA
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If ordering rules are relaxed, it must be assumed that accesses done inside an
|
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interrupt disabled section may leak outside of it and may interleave with
|
|
accesses performed in an interrupt - and vice versa - unless implicit or
|
|
explicit barriers are used.
|
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Normally this won't be a problem because the I/O accesses done inside such
|
|
sections will include synchronous load operations on strictly ordered I/O
|
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registers that form implicit I/O barriers. If this isn't sufficient then an
|
|
mmiowb() may need to be used explicitly.
|
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|
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|
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A similar situation may occur between an interrupt routine and two routines
|
|
running on separate CPUs that communicate with each other. If such a case is
|
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likely, then interrupt-disabling locks should be used to guarantee ordering.
|
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|
|
|
|
==========================
|
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KERNEL I/O BARRIER EFFECTS
|
|
==========================
|
|
|
|
When accessing I/O memory, drivers should use the appropriate accessor
|
|
functions:
|
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|
|
(*) inX(), outX():
|
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|
|
These are intended to talk to I/O space rather than memory space, but
|
|
that's primarily a CPU-specific concept. The i386 and x86_64 processors do
|
|
indeed have special I/O space access cycles and instructions, but many
|
|
CPUs don't have such a concept.
|
|
|
|
The PCI bus, amongst others, defines an I/O space concept which - on such
|
|
CPUs as i386 and x86_64 - readily maps to the CPU's concept of I/O
|
|
space. However, it may also be mapped as a virtual I/O space in the CPU's
|
|
memory map, particularly on those CPUs that don't support alternate I/O
|
|
spaces.
|
|
|
|
Accesses to this space may be fully synchronous (as on i386), but
|
|
intermediary bridges (such as the PCI host bridge) may not fully honour
|
|
that.
|
|
|
|
They are guaranteed to be fully ordered with respect to each other.
|
|
|
|
They are not guaranteed to be fully ordered with respect to other types of
|
|
memory and I/O operation.
|
|
|
|
(*) readX(), writeX():
|
|
|
|
Whether these are guaranteed to be fully ordered and uncombined with
|
|
respect to each other on the issuing CPU depends on the characteristics
|
|
defined for the memory window through which they're accessing. On later
|
|
i386 architecture machines, for example, this is controlled by way of the
|
|
MTRR registers.
|
|
|
|
Ordinarily, these will be guaranteed to be fully ordered and uncombined,
|
|
provided they're not accessing a prefetchable device.
|
|
|
|
However, intermediary hardware (such as a PCI bridge) may indulge in
|
|
deferral if it so wishes; to flush a store, a load from the same location
|
|
is preferred[*], but a load from the same device or from configuration
|
|
space should suffice for PCI.
|
|
|
|
[*] NOTE! attempting to load from the same location as was written to may
|
|
cause a malfunction - consider the 16550 Rx/Tx serial registers for
|
|
example.
|
|
|
|
Used with prefetchable I/O memory, an mmiowb() barrier may be required to
|
|
force stores to be ordered.
|
|
|
|
Please refer to the PCI specification for more information on interactions
|
|
between PCI transactions.
|
|
|
|
(*) readX_relaxed()
|
|
|
|
These are similar to readX(), but are not guaranteed to be ordered in any
|
|
way. Be aware that there is no I/O read barrier available.
|
|
|
|
(*) ioreadX(), iowriteX()
|
|
|
|
These will perform appropriately for the type of access they're actually
|
|
doing, be it inX()/outX() or readX()/writeX().
|
|
|
|
|
|
========================================
|
|
ASSUMED MINIMUM EXECUTION ORDERING MODEL
|
|
========================================
|
|
|
|
It has to be assumed that the conceptual CPU is weakly-ordered but that it will
|
|
maintain the appearance of program causality with respect to itself. Some CPUs
|
|
(such as i386 or x86_64) are more constrained than others (such as powerpc or
|
|
frv), and so the most relaxed case (namely DEC Alpha) must be assumed outside
|
|
of arch-specific code.
|
|
|
|
This means that it must be considered that the CPU will execute its instruction
|
|
stream in any order it feels like - or even in parallel - provided that if an
|
|
instruction in the stream depends on an earlier instruction, then that
|
|
earlier instruction must be sufficiently complete[*] before the later
|
|
instruction may proceed; in other words: provided that the appearance of
|
|
causality is maintained.
|
|
|
|
[*] Some instructions have more than one effect - such as changing the
|
|
condition codes, changing registers or changing memory - and different
|
|
instructions may depend on different effects.
|
|
|
|
A CPU may also discard any instruction sequence that winds up having no
|
|
ultimate effect. For example, if two adjacent instructions both load an
|
|
immediate value into the same register, the first may be discarded.
|
|
|
|
|
|
Similarly, it has to be assumed that compiler might reorder the instruction
|
|
stream in any way it sees fit, again provided the appearance of causality is
|
|
maintained.
|
|
|
|
|
|
============================
|
|
THE EFFECTS OF THE CPU CACHE
|
|
============================
|
|
|
|
The way cached memory operations are perceived across the system is affected to
|
|
a certain extent by the caches that lie between CPUs and memory, and by the
|
|
memory coherence system that maintains the consistency of state in the system.
|
|
|
|
As far as the way a CPU interacts with another part of the system through the
|
|
caches goes, the memory system has to include the CPU's caches, and memory
|
|
barriers for the most part act at the interface between the CPU and its cache
|
|
(memory barriers logically act on the dotted line in the following diagram):
|
|
|
|
<--- CPU ---> : <----------- Memory ----------->
|
|
:
|
|
+--------+ +--------+ : +--------+ +-----------+
|
|
| | | | : | | | | +--------+
|
|
| CPU | | Memory | : | CPU | | | | |
|
|
| Core |--->| Access |----->| Cache |<-->| | | |
|
|
| | | Queue | : | | | |--->| Memory |
|
|
| | | | : | | | | | |
|
|
+--------+ +--------+ : +--------+ | | | |
|
|
: | Cache | +--------+
|
|
: | Coherency |
|
|
: | Mechanism | +--------+
|
|
+--------+ +--------+ : +--------+ | | | |
|
|
| | | | : | | | | | |
|
|
| CPU | | Memory | : | CPU | | |--->| Device |
|
|
| Core |--->| Access |----->| Cache |<-->| | | |
|
|
| | | Queue | : | | | | | |
|
|
| | | | : | | | | +--------+
|
|
+--------+ +--------+ : +--------+ +-----------+
|
|
:
|
|
:
|
|
|
|
Although any particular load or store may not actually appear outside of the
|
|
CPU that issued it since it may have been satisfied within the CPU's own cache,
|
|
it will still appear as if the full memory access had taken place as far as the
|
|
other CPUs are concerned since the cache coherency mechanisms will migrate the
|
|
cacheline over to the accessing CPU and propagate the effects upon conflict.
|
|
|
|
The CPU core may execute instructions in any order it deems fit, provided the
|
|
expected program causality appears to be maintained. Some of the instructions
|
|
generate load and store operations which then go into the queue of memory
|
|
accesses to be performed. The core may place these in the queue in any order
|
|
it wishes, and continue execution until it is forced to wait for an instruction
|
|
to complete.
|
|
|
|
What memory barriers are concerned with is controlling the order in which
|
|
accesses cross from the CPU side of things to the memory side of things, and
|
|
the order in which the effects are perceived to happen by the other observers
|
|
in the system.
|
|
|
|
[!] Memory barriers are _not_ needed within a given CPU, as CPUs always see
|
|
their own loads and stores as if they had happened in program order.
|
|
|
|
[!] MMIO or other device accesses may bypass the cache system. This depends on
|
|
the properties of the memory window through which devices are accessed and/or
|
|
the use of any special device communication instructions the CPU may have.
|
|
|
|
|
|
CACHE COHERENCY
|
|
---------------
|
|
|
|
Life isn't quite as simple as it may appear above, however: for while the
|
|
caches are expected to be coherent, there's no guarantee that that coherency
|
|
will be ordered. This means that whilst changes made on one CPU will
|
|
eventually become visible on all CPUs, there's no guarantee that they will
|
|
become apparent in the same order on those other CPUs.
|
|
|
|
|
|
Consider dealing with a system that has a pair of CPUs (1 & 2), each of which
|
|
has a pair of parallel data caches (CPU 1 has A/B, and CPU 2 has C/D):
|
|
|
|
:
|
|
: +--------+
|
|
: +---------+ | |
|
|
+--------+ : +--->| Cache A |<------->| |
|
|
| | : | +---------+ | |
|
|
| CPU 1 |<---+ | |
|
|
| | : | +---------+ | |
|
|
+--------+ : +--->| Cache B |<------->| |
|
|
: +---------+ | |
|
|
: | Memory |
|
|
: +---------+ | System |
|
|
+--------+ : +--->| Cache C |<------->| |
|
|
| | : | +---------+ | |
|
|
| CPU 2 |<---+ | |
|
|
| | : | +---------+ | |
|
|
+--------+ : +--->| Cache D |<------->| |
|
|
: +---------+ | |
|
|
: +--------+
|
|
:
|
|
|
|
Imagine the system has the following properties:
|
|
|
|
(*) an odd-numbered cache line may be in cache A, cache C or it may still be
|
|
resident in memory;
|
|
|
|
(*) an even-numbered cache line may be in cache B, cache D or it may still be
|
|
resident in memory;
|
|
|
|
(*) whilst the CPU core is interrogating one cache, the other cache may be
|
|
making use of the bus to access the rest of the system - perhaps to
|
|
displace a dirty cacheline or to do a speculative load;
|
|
|
|
(*) each cache has a queue of operations that need to be applied to that cache
|
|
to maintain coherency with the rest of the system;
|
|
|
|
(*) the coherency queue is not flushed by normal loads to lines already
|
|
present in the cache, even though the contents of the queue may
|
|
potentially affect those loads.
|
|
|
|
Imagine, then, that two writes are made on the first CPU, with a write barrier
|
|
between them to guarantee that they will appear to reach that CPU's caches in
|
|
the requisite order:
|
|
|
|
CPU 1 CPU 2 COMMENT
|
|
=============== =============== =======================================
|
|
u == 0, v == 1 and p == &u, q == &u
|
|
v = 2;
|
|
smp_wmb(); Make sure change to v is visible before
|
|
change to p
|
|
<A:modify v=2> v is now in cache A exclusively
|
|
p = &v;
|
|
<B:modify p=&v> p is now in cache B exclusively
|
|
|
|
The write memory barrier forces the other CPUs in the system to perceive that
|
|
the local CPU's caches have apparently been updated in the correct order. But
|
|
now imagine that the second CPU wants to read those values:
|
|
|
|
CPU 1 CPU 2 COMMENT
|
|
=============== =============== =======================================
|
|
...
|
|
q = p;
|
|
x = *q;
|
|
|
|
The above pair of reads may then fail to happen in the expected order, as the
|
|
cacheline holding p may get updated in one of the second CPU's caches whilst
|
|
the update to the cacheline holding v is delayed in the other of the second
|
|
CPU's caches by some other cache event:
|
|
|
|
CPU 1 CPU 2 COMMENT
|
|
=============== =============== =======================================
|
|
u == 0, v == 1 and p == &u, q == &u
|
|
v = 2;
|
|
smp_wmb();
|
|
<A:modify v=2> <C:busy>
|
|
<C:queue v=2>
|
|
p = &v; q = p;
|
|
<D:request p>
|
|
<B:modify p=&v> <D:commit p=&v>
|
|
<D:read p>
|
|
x = *q;
|
|
<C:read *q> Reads from v before v updated in cache
|
|
<C:unbusy>
|
|
<C:commit v=2>
|
|
|
|
Basically, whilst both cachelines will be updated on CPU 2 eventually, there's
|
|
no guarantee that, without intervention, the order of update will be the same
|
|
as that committed on CPU 1.
|
|
|
|
|
|
To intervene, we need to interpolate a data dependency barrier or a read
|
|
barrier between the loads. This will force the cache to commit its coherency
|
|
queue before processing any further requests:
|
|
|
|
CPU 1 CPU 2 COMMENT
|
|
=============== =============== =======================================
|
|
u == 0, v == 1 and p == &u, q == &u
|
|
v = 2;
|
|
smp_wmb();
|
|
<A:modify v=2> <C:busy>
|
|
<C:queue v=2>
|
|
p = &v; q = p;
|
|
<D:request p>
|
|
<B:modify p=&v> <D:commit p=&v>
|
|
<D:read p>
|
|
smp_read_barrier_depends()
|
|
<C:unbusy>
|
|
<C:commit v=2>
|
|
x = *q;
|
|
<C:read *q> Reads from v after v updated in cache
|
|
|
|
|
|
This sort of problem can be encountered on DEC Alpha processors as they have a
|
|
split cache that improves performance by making better use of the data bus.
|
|
Whilst most CPUs do imply a data dependency barrier on the read when a memory
|
|
access depends on a read, not all do, so it may not be relied on.
|
|
|
|
Other CPUs may also have split caches, but must coordinate between the various
|
|
cachelets for normal memory accesses. The semantics of the Alpha removes the
|
|
need for coordination in the absence of memory barriers.
|
|
|
|
|
|
CACHE COHERENCY VS DMA
|
|
----------------------
|
|
|
|
Not all systems maintain cache coherency with respect to devices doing DMA. In
|
|
such cases, a device attempting DMA may obtain stale data from RAM because
|
|
dirty cache lines may be resident in the caches of various CPUs, and may not
|
|
have been written back to RAM yet. To deal with this, the appropriate part of
|
|
the kernel must flush the overlapping bits of cache on each CPU (and maybe
|
|
invalidate them as well).
|
|
|
|
In addition, the data DMA'd to RAM by a device may be overwritten by dirty
|
|
cache lines being written back to RAM from a CPU's cache after the device has
|
|
installed its own data, or cache lines present in the CPU's cache may simply
|
|
obscure the fact that RAM has been updated, until at such time as the cacheline
|
|
is discarded from the CPU's cache and reloaded. To deal with this, the
|
|
appropriate part of the kernel must invalidate the overlapping bits of the
|
|
cache on each CPU.
|
|
|
|
See Documentation/cachetlb.txt for more information on cache management.
|
|
|
|
|
|
CACHE COHERENCY VS MMIO
|
|
-----------------------
|
|
|
|
Memory mapped I/O usually takes place through memory locations that are part of
|
|
a window in the CPU's memory space that has different properties assigned than
|
|
the usual RAM directed window.
|
|
|
|
Amongst these properties is usually the fact that such accesses bypass the
|
|
caching entirely and go directly to the device buses. This means MMIO accesses
|
|
may, in effect, overtake accesses to cached memory that were emitted earlier.
|
|
A memory barrier isn't sufficient in such a case, but rather the cache must be
|
|
flushed between the cached memory write and the MMIO access if the two are in
|
|
any way dependent.
|
|
|
|
|
|
=========================
|
|
THE THINGS CPUS GET UP TO
|
|
=========================
|
|
|
|
A programmer might take it for granted that the CPU will perform memory
|
|
operations in exactly the order specified, so that if the CPU is, for example,
|
|
given the following piece of code to execute:
|
|
|
|
a = *A;
|
|
*B = b;
|
|
c = *C;
|
|
d = *D;
|
|
*E = e;
|
|
|
|
they would then expect that the CPU will complete the memory operation for each
|
|
instruction before moving on to the next one, leading to a definite sequence of
|
|
operations as seen by external observers in the system:
|
|
|
|
LOAD *A, STORE *B, LOAD *C, LOAD *D, STORE *E.
|
|
|
|
|
|
Reality is, of course, much messier. With many CPUs and compilers, the above
|
|
assumption doesn't hold because:
|
|
|
|
(*) loads are more likely to need to be completed immediately to permit
|
|
execution progress, whereas stores can often be deferred without a
|
|
problem;
|
|
|
|
(*) loads may be done speculatively, and the result discarded should it prove
|
|
to have been unnecessary;
|
|
|
|
(*) loads may be done speculatively, leading to the result having been fetched
|
|
at the wrong time in the expected sequence of events;
|
|
|
|
(*) the order of the memory accesses may be rearranged to promote better use
|
|
of the CPU buses and caches;
|
|
|
|
(*) loads and stores may be combined to improve performance when talking to
|
|
memory or I/O hardware that can do batched accesses of adjacent locations,
|
|
thus cutting down on transaction setup costs (memory and PCI devices may
|
|
both be able to do this); and
|
|
|
|
(*) the CPU's data cache may affect the ordering, and whilst cache-coherency
|
|
mechanisms may alleviate this - once the store has actually hit the cache
|
|
- there's no guarantee that the coherency management will be propagated in
|
|
order to other CPUs.
|
|
|
|
So what another CPU, say, might actually observe from the above piece of code
|
|
is:
|
|
|
|
LOAD *A, ..., LOAD {*C,*D}, STORE *E, STORE *B
|
|
|
|
(Where "LOAD {*C,*D}" is a combined load)
|
|
|
|
|
|
However, it is guaranteed that a CPU will be self-consistent: it will see its
|
|
_own_ accesses appear to be correctly ordered, without the need for a memory
|
|
barrier. For instance with the following code:
|
|
|
|
U = *A;
|
|
*A = V;
|
|
*A = W;
|
|
X = *A;
|
|
*A = Y;
|
|
Z = *A;
|
|
|
|
and assuming no intervention by an external influence, it can be assumed that
|
|
the final result will appear to be:
|
|
|
|
U == the original value of *A
|
|
X == W
|
|
Z == Y
|
|
*A == Y
|
|
|
|
The code above may cause the CPU to generate the full sequence of memory
|
|
accesses:
|
|
|
|
U=LOAD *A, STORE *A=V, STORE *A=W, X=LOAD *A, STORE *A=Y, Z=LOAD *A
|
|
|
|
in that order, but, without intervention, the sequence may have almost any
|
|
combination of elements combined or discarded, provided the program's view of
|
|
the world remains consistent.
|
|
|
|
The compiler may also combine, discard or defer elements of the sequence before
|
|
the CPU even sees them.
|
|
|
|
For instance:
|
|
|
|
*A = V;
|
|
*A = W;
|
|
|
|
may be reduced to:
|
|
|
|
*A = W;
|
|
|
|
since, without a write barrier, it can be assumed that the effect of the
|
|
storage of V to *A is lost. Similarly:
|
|
|
|
*A = Y;
|
|
Z = *A;
|
|
|
|
may, without a memory barrier, be reduced to:
|
|
|
|
*A = Y;
|
|
Z = Y;
|
|
|
|
and the LOAD operation never appear outside of the CPU.
|
|
|
|
|
|
AND THEN THERE'S THE ALPHA
|
|
--------------------------
|
|
|
|
The DEC Alpha CPU is one of the most relaxed CPUs there is. Not only that,
|
|
some versions of the Alpha CPU have a split data cache, permitting them to have
|
|
two semantically-related cache lines updated at separate times. This is where
|
|
the data dependency barrier really becomes necessary as this synchronises both
|
|
caches with the memory coherence system, thus making it seem like pointer
|
|
changes vs new data occur in the right order.
|
|
|
|
The Alpha defines the Linux kernel's memory barrier model.
|
|
|
|
See the subsection on "Cache Coherency" above.
|
|
|
|
|
|
==========
|
|
REFERENCES
|
|
==========
|
|
|
|
Alpha AXP Architecture Reference Manual, Second Edition (Sites & Witek,
|
|
Digital Press)
|
|
Chapter 5.2: Physical Address Space Characteristics
|
|
Chapter 5.4: Caches and Write Buffers
|
|
Chapter 5.5: Data Sharing
|
|
Chapter 5.6: Read/Write Ordering
|
|
|
|
AMD64 Architecture Programmer's Manual Volume 2: System Programming
|
|
Chapter 7.1: Memory-Access Ordering
|
|
Chapter 7.4: Buffering and Combining Memory Writes
|
|
|
|
IA-32 Intel Architecture Software Developer's Manual, Volume 3:
|
|
System Programming Guide
|
|
Chapter 7.1: Locked Atomic Operations
|
|
Chapter 7.2: Memory Ordering
|
|
Chapter 7.4: Serializing Instructions
|
|
|
|
The SPARC Architecture Manual, Version 9
|
|
Chapter 8: Memory Models
|
|
Appendix D: Formal Specification of the Memory Models
|
|
Appendix J: Programming with the Memory Models
|
|
|
|
UltraSPARC Programmer Reference Manual
|
|
Chapter 5: Memory Accesses and Cacheability
|
|
Chapter 15: Sparc-V9 Memory Models
|
|
|
|
UltraSPARC III Cu User's Manual
|
|
Chapter 9: Memory Models
|
|
|
|
UltraSPARC IIIi Processor User's Manual
|
|
Chapter 8: Memory Models
|
|
|
|
UltraSPARC Architecture 2005
|
|
Chapter 9: Memory
|
|
Appendix D: Formal Specifications of the Memory Models
|
|
|
|
UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005
|
|
Chapter 8: Memory Models
|
|
Appendix F: Caches and Cache Coherency
|
|
|
|
Solaris Internals, Core Kernel Architecture, p63-68:
|
|
Chapter 3.3: Hardware Considerations for Locks and
|
|
Synchronization
|
|
|
|
Unix Systems for Modern Architectures, Symmetric Multiprocessing and Caching
|
|
for Kernel Programmers:
|
|
Chapter 13: Other Memory Models
|
|
|
|
Intel Itanium Architecture Software Developer's Manual: Volume 1:
|
|
Section 2.6: Speculation
|
|
Section 4.4: Memory Access
|