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1004165f34
The XLP USB controller appears as a device on the internal SoC PCIe
bus, the block has 2 EHCI blocks and 4 OHCI blocks. Change are to:
* Add files netlogic/xlp/usb-init.c and asm/netlogic/xlp-hal/usb.h
to initialize the USB controller and define PCI fixups. The PCI
fixups are to setup interrupts and DMA mask.
* Update include/asm/xlp-hal/{iomap.h,pic.h,xlp.h} to add interrupt
mapping for EHCI/OHCI interrupts.
Signed-off-by: Ganesan Ramalingam <ganesanr@netlogicmicro.com>
Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3756/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
125 lines
3.9 KiB
C
125 lines
3.9 KiB
C
/*
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* Copyright (c) 2003-2012 Broadcom Corporation
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* All Rights Reserved
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the Broadcom
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* license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/dma-mapping.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <asm/netlogic/haldefs.h>
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#include <asm/netlogic/xlp-hal/iomap.h>
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#include <asm/netlogic/xlp-hal/xlp.h>
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#include <asm/netlogic/xlp-hal/usb.h>
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static void nlm_usb_intr_en(int node, int port)
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{
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uint32_t val;
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uint64_t port_addr;
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port_addr = nlm_get_usb_regbase(node, port);
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val = nlm_read_usb_reg(port_addr, USB_INT_EN);
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val = USB_CTRL_INTERRUPT_EN | USB_OHCI_INTERRUPT_EN |
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USB_OHCI_INTERRUPT1_EN | USB_CTRL_INTERRUPT_EN |
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USB_OHCI_INTERRUPT_EN | USB_OHCI_INTERRUPT2_EN;
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nlm_write_usb_reg(port_addr, USB_INT_EN, val);
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}
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static void nlm_usb_hw_reset(int node, int port)
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{
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uint64_t port_addr;
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uint32_t val;
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/* reset USB phy */
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port_addr = nlm_get_usb_regbase(node, port);
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val = nlm_read_usb_reg(port_addr, USB_PHY_0);
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val &= ~(USB_PHY_RESET | USB_PHY_PORT_RESET_0 | USB_PHY_PORT_RESET_1);
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nlm_write_usb_reg(port_addr, USB_PHY_0, val);
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mdelay(100);
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val = nlm_read_usb_reg(port_addr, USB_CTL_0);
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val &= ~(USB_CONTROLLER_RESET);
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val |= 0x4;
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nlm_write_usb_reg(port_addr, USB_CTL_0, val);
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}
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static int __init nlm_platform_usb_init(void)
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{
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pr_info("Initializing USB Interface\n");
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nlm_usb_hw_reset(0, 0);
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nlm_usb_hw_reset(0, 3);
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/* Enable PHY interrupts */
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nlm_usb_intr_en(0, 0);
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nlm_usb_intr_en(0, 3);
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return 0;
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}
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arch_initcall(nlm_platform_usb_init);
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static u64 xlp_usb_dmamask = ~(u32)0;
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/* Fixup the IRQ for USB devices which is exist on XLP SOC PCIE bus */
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static void nlm_usb_fixup_final(struct pci_dev *dev)
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{
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dev->dev.dma_mask = &xlp_usb_dmamask;
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dev->dev.coherent_dma_mask = DMA_BIT_MASK(64);
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switch (dev->devfn) {
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case 0x10:
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dev->irq = PIC_EHCI_0_IRQ;
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break;
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case 0x11:
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dev->irq = PIC_OHCI_0_IRQ;
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break;
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case 0x12:
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dev->irq = PIC_OHCI_1_IRQ;
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break;
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case 0x13:
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dev->irq = PIC_EHCI_1_IRQ;
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break;
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case 0x14:
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dev->irq = PIC_OHCI_2_IRQ;
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break;
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case 0x15:
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dev->irq = PIC_OHCI_3_IRQ;
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break;
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}
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_EHCI,
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nlm_usb_fixup_final);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_OHCI,
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nlm_usb_fixup_final);
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