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300459d558
IPI registers of Loongson-3 include IPI_SET, IPI_CLEAR, IPI_STATUS,
IPI_EN and IPI_MAILBOX_BUF. Each bit of IPI_STATUS indicate a type of
IPI and IPI_EN indicate whether the IPI is enabled. The sender write 1
to IPI_SET bits generate IPIs in IPI_STATUS, and receiver write 1 to
bits of IPI_CLEAR to clear IPIs. IPI_MAILBOX_BUF are used to deliver
more information about IPIs.
Why we change code in arch/mips/loongson/common/setup.c?
If without this change, when SMP configured, system cannot boot since
it hang at printk() in cgroup_init_early(). The root cause is:
console_trylock()
\-->down_trylock(&console_sem)
\-->raw_spin_unlock_irqrestore(&sem->lock, flags)
\-->_raw_spin_unlock_irqrestore()(SMP/UP have different versions)
\-->__raw_spin_unlock_irqrestore() (following is the SMP case)
\-->do_raw_spin_unlock()
\-->arch_spin_unlock()
\-->nudge_writes()
\-->mb()
\-->wbflush()
\-->__wbflush()
In previous code __wbflush() is initialized in plat_mem_setup(), but
cgroup_init_early() is called before plat_mem_setup(). Therefore, In
this patch we make changes to avoid boot failure.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Hongliang Tao <taohl@lemote.com>
Signed-off-by: Hua Yan <yanh@lemote.com>
Tested-by: Alex Smith <alex.smith@imgtec.com>
Reviewed-by: Alex Smith <alex.smith@imgtec.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/6638
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
117 lines
2.7 KiB
C
117 lines
2.7 KiB
C
#include <loongson.h>
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#include <irq.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <asm/irq_cpu.h>
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#include <asm/i8259.h>
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#include <asm/mipsregs.h>
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unsigned int ht_irq[] = {1, 3, 4, 5, 6, 7, 8, 12, 14, 15};
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static void ht_irqdispatch(void)
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{
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unsigned int i, irq;
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irq = LOONGSON_HT1_INT_VECTOR(0);
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LOONGSON_HT1_INT_VECTOR(0) = irq; /* Acknowledge the IRQs */
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for (i = 0; i < ARRAY_SIZE(ht_irq); i++) {
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if (irq & (0x1 << ht_irq[i]))
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do_IRQ(ht_irq[i]);
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}
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}
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void mach_irq_dispatch(unsigned int pending)
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{
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if (pending & CAUSEF_IP7)
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do_IRQ(LOONGSON_TIMER_IRQ);
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#if defined(CONFIG_SMP)
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else if (pending & CAUSEF_IP6)
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loongson3_ipi_interrupt(NULL);
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#endif
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else if (pending & CAUSEF_IP3)
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ht_irqdispatch();
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else if (pending & CAUSEF_IP2)
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do_IRQ(LOONGSON_UART_IRQ);
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else {
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pr_err("%s : spurious interrupt\n", __func__);
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spurious_interrupt();
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}
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}
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static struct irqaction cascade_irqaction = {
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.handler = no_action,
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.name = "cascade",
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};
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static inline void mask_loongson_irq(struct irq_data *d)
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{
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clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
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irq_disable_hazard();
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/* Workaround: UART IRQ may deliver to any core */
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if (d->irq == LOONGSON_UART_IRQ) {
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int cpu = smp_processor_id();
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LOONGSON_INT_ROUTER_INTENCLR = 1 << 10;
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LOONGSON_INT_ROUTER_LPC = 0x10 + (1<<cpu);
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}
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}
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static inline void unmask_loongson_irq(struct irq_data *d)
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{
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/* Workaround: UART IRQ may deliver to any core */
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if (d->irq == LOONGSON_UART_IRQ) {
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int cpu = smp_processor_id();
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LOONGSON_INT_ROUTER_INTENSET = 1 << 10;
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LOONGSON_INT_ROUTER_LPC = 0x10 + (1<<cpu);
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}
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set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
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irq_enable_hazard();
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}
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/* For MIPS IRQs which shared by all cores */
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static struct irq_chip loongson_irq_chip = {
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.name = "Loongson",
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.irq_ack = mask_loongson_irq,
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.irq_mask = mask_loongson_irq,
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.irq_mask_ack = mask_loongson_irq,
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.irq_unmask = unmask_loongson_irq,
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.irq_eoi = unmask_loongson_irq,
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};
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void irq_router_init(void)
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{
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int i;
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/* route LPC int to cpu core0 int 0 */
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LOONGSON_INT_ROUTER_LPC = LOONGSON_INT_CORE0_INT0;
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/* route HT1 int0 ~ int7 to cpu core0 INT1*/
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for (i = 0; i < 8; i++)
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LOONGSON_INT_ROUTER_HT1(i) = LOONGSON_INT_CORE0_INT1;
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/* enable HT1 interrupt */
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LOONGSON_HT1_INTN_EN(0) = 0xffffffff;
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/* enable router interrupt intenset */
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LOONGSON_INT_ROUTER_INTENSET =
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LOONGSON_INT_ROUTER_INTEN | (0xffff << 16) | 0x1 << 10;
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}
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void __init mach_init_irq(void)
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{
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clear_c0_status(ST0_IM | ST0_BEV);
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irq_router_init();
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mips_cpu_irq_init();
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init_i8259_irqs();
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irq_set_chip_and_handler(LOONGSON_UART_IRQ,
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&loongson_irq_chip, handle_level_irq);
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/* setup HT1 irq */
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setup_irq(LOONGSON_HT1_IRQ, &cascade_irqaction);
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set_c0_status(STATUSF_IP2 | STATUSF_IP6);
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}
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