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8578953687
These are the main MIPS changes for 4.16. Rough overview: - Basic support for the Ingenic JZ4770 based GCW Zero open-source handheld video game console - Support for the Ranchu board (used by Android emulator) - Various cleanups and misc improvements Fixes: - Fix generic platform's USB_*HCI_BIG_ENDIAN selects (4.9) - Fix vmlinuz default build when ZBOOT selected - Fix clean up of vmlinuz targets - Fix command line duplication (in preparation for Ingenic JZ4770) Miscellaneous: - Allow Processor ID reads to be to be optimised away by the compiler (improves performance when running in guest) - Push ARCH_MIGHT_HAVE_PC_SERIO/PARPORT down to platform level to disable on generic platform with Ranchu board support - Add helpers for assembler macro instructions for older assemblers - Use assembler macro instructions to support VZ, XPA & MSA operations on older assemblers, removing C wrapper duplication - Various improvements to VZ & XPA assembly wrappers - Add drivers/platform/mips/ to MIPS MAINTAINERS entry Minor cleanups: - Misc FPU emulation cleanups (removal of unnecessary include, moving macros to common header, checkpatch and sparse fixes) - Remove duplicate assignment of core in play_dead() - Remove duplication in watchpoint handling - Remove mips_dma_mapping_error() stub - Use NULL instead of 0 in prepare_ftrace_return() - Use proper kernel-doc Return keyword for __compute_return_epc_for_insn() - Remove duplicate semicolon in csum_fold() Platform support: Broadcom: - Enable ZBOOT on BCM47xx Generic platform: - Add Ranchu board support, used by Android emulator - Fix machine compatible string matching for Ranchu - Support GIC in EIC mode Ingenic platforms: - Add DT, defconfig and other support for JZ4770 SoC and GCW Zero - Support dynamnic machine types (i.e. JZ4740 / JZ4770 / JZ4780) - Add Ingenic JZ4770 CGU clocks - General Ingenic clk changes to prepare for JZ4770 SoC support - Use common command line handling code - Add DT vendor prefix to GCW (Game Consoles Worldwide) Loongson: - Add MAINTAINERS entry for Loongson2 and Loongson3 platforms - Drop 32-bit support for Loongson 2E/2F devices - Fix build failures due to multiple use of "MEM_RESERVED" -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEd80NauSabkiESfLYbAtpk944dnoFAlp64ZUACgkQbAtpk944 dnrXrg//UPWeZMye/uHw0eEeJJjybyA0IWpJ6M94gbHxpduhQsjYU3CR9U4ZBmhs feY53dahh0RCR0k28EF8DEPkoUbGFKmyYCnvqAuatq1XOjAZtlgS9+VVzbK+Iswm XkZD1MBoZ49o0meyjQrH/2Ri/t6tHuzo0G2WtRJ8FnVruN9ymG6D5pR4Y31gDucb 6JkTXjNfRJIKd0qJgP+c3HdlKE7jlnCTJnzHdA+5FbZVwKbm2/6KxbQo5Gc1BXJX 4j7I4nJ0FIz0cB6fHbcccFSW9w3lPa9bQ4XpYPJYE6a36QldFvMWHRxvI6rxrACN 5mPqIB9uqvtW8sdUbJtNRXFlNnm8XZzvsNqP6WxGQPW70+q2camni9W/gC1ifQsF +uVV54yj3Ky8xQNbbpfbDp/tFXRuLtj3DV4/a3dwA5J0YGEuMn1zzV5WTTzymFVn 3NKl62LDUlzBNw0d1lUPMY6P1oKcNnRhLxBq0cxaB7AdOLF0jlCQ/wYUhXPpblj6 CQB4cupR4IMvL7FZ1RS98e1RHaF8mXpaZBnGXT251DxZEre9OXCJxDdzqemedTVi SaCcvQqApCQD8OihL+wHZLew8Vp4EvwGAa++Evu/Ot4rWjY/9MGLtewYk8jkOEf6 qk30dDn86ou29HNwpzfWadIq5Zew+QftifGOzTcuzgrJXXt+jH8= =7iwT -----END PGP SIGNATURE----- Merge tag 'mips_4.16' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips Pull MIPS updates from James Hogan: "These are the main MIPS changes for 4.16. Rough overview: (1) Basic support for the Ingenic JZ4770 based GCW Zero open-source handheld video game console (2) Support for the Ranchu board (used by Android emulator) (3) Various cleanups and misc improvements More detailed summary: Fixes: - Fix generic platform's USB_*HCI_BIG_ENDIAN selects (4.9) - Fix vmlinuz default build when ZBOOT selected - Fix clean up of vmlinuz targets - Fix command line duplication (in preparation for Ingenic JZ4770) Miscellaneous: - Allow Processor ID reads to be to be optimised away by the compiler (improves performance when running in guest) - Push ARCH_MIGHT_HAVE_PC_SERIO/PARPORT down to platform level to disable on generic platform with Ranchu board support - Add helpers for assembler macro instructions for older assemblers - Use assembler macro instructions to support VZ, XPA & MSA operations on older assemblers, removing C wrapper duplication - Various improvements to VZ & XPA assembly wrappers - Add drivers/platform/mips/ to MIPS MAINTAINERS entry Minor cleanups: - Misc FPU emulation cleanups (removal of unnecessary include, moving macros to common header, checkpatch and sparse fixes) - Remove duplicate assignment of core in play_dead() - Remove duplication in watchpoint handling - Remove mips_dma_mapping_error() stub - Use NULL instead of 0 in prepare_ftrace_return() - Use proper kernel-doc Return keyword for __compute_return_epc_for_insn() - Remove duplicate semicolon in csum_fold() Platform support: Broadcom: - Enable ZBOOT on BCM47xx Generic platform: - Add Ranchu board support, used by Android emulator - Fix machine compatible string matching for Ranchu - Support GIC in EIC mode Ingenic platforms: - Add DT, defconfig and other support for JZ4770 SoC and GCW Zero - Support dynamnic machine types (i.e. JZ4740 / JZ4770 / JZ4780) - Add Ingenic JZ4770 CGU clocks - General Ingenic clk changes to prepare for JZ4770 SoC support - Use common command line handling code - Add DT vendor prefix to GCW (Game Consoles Worldwide) Loongson: - Add MAINTAINERS entry for Loongson2 and Loongson3 platforms - Drop 32-bit support for Loongson 2E/2F devices - Fix build failures due to multiple use of 'MEM_RESERVED'" * tag 'mips_4.16' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips: (53 commits) MIPS: Malta: Sanitize mouse and keyboard configuration. MIPS: Update defconfigs after previous patch. MIPS: Push ARCH_MIGHT_HAVE_PC_SERIO down to platform level MIPS: Push ARCH_MIGHT_HAVE_PC_PARPORT down to platform level MIPS: SMP-CPS: Remove duplicate assignment of core in play_dead MIPS: Generic: Support GIC in EIC mode MIPS: generic: Fix Makefile alignment MIPS: generic: Fix ranchu_of_match[] termination MIPS: generic: Fix machine compatible matching MIPS: Loongson fix name confict - MEM_RESERVED MIPS: bcm47xx: enable ZBOOT support MIPS: Fix trailing semicolon MIPS: Watch: Avoid duplication of bits in mips_read_watch_registers MIPS: Watch: Avoid duplication of bits in mips_install_watch_registers. MIPS: MSA: Update helpers to use new asm macros MIPS: XPA: Standardise readx/writex accessors MIPS: XPA: Allow use of $0 (zero) to MTHC0 MIPS: XPA: Use XPA instructions in assembly MIPS: VZ: Pass GC0 register names in $n format MIPS: VZ: Update helpers to use new asm macros ...
415 lines
11 KiB
C
415 lines
11 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2000 Ani Joshi <ajoshi@unixbox.com>
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* Copyright (C) 2000, 2001, 06 Ralf Baechle <ralf@linux-mips.org>
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* swiped from i386, and cloned for MIPS by Geert, polished by Ralf.
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*/
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#include <linux/types.h>
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#include <linux/dma-mapping.h>
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#include <linux/mm.h>
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#include <linux/export.h>
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#include <linux/scatterlist.h>
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#include <linux/string.h>
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#include <linux/gfp.h>
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#include <linux/highmem.h>
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#include <linux/dma-contiguous.h>
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#include <asm/cache.h>
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#include <asm/cpu-type.h>
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#include <asm/io.h>
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#include <dma-coherence.h>
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#if defined(CONFIG_DMA_MAYBE_COHERENT) && !defined(CONFIG_DMA_PERDEV_COHERENT)
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/* User defined DMA coherency from command line. */
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enum coherent_io_user_state coherentio = IO_COHERENCE_DEFAULT;
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EXPORT_SYMBOL_GPL(coherentio);
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int hw_coherentio = 0; /* Actual hardware supported DMA coherency setting. */
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static int __init setcoherentio(char *str)
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{
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coherentio = IO_COHERENCE_ENABLED;
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pr_info("Hardware DMA cache coherency (command line)\n");
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return 0;
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}
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early_param("coherentio", setcoherentio);
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static int __init setnocoherentio(char *str)
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{
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coherentio = IO_COHERENCE_DISABLED;
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pr_info("Software DMA cache coherency (command line)\n");
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return 0;
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}
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early_param("nocoherentio", setnocoherentio);
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#endif
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static inline struct page *dma_addr_to_page(struct device *dev,
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dma_addr_t dma_addr)
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{
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return pfn_to_page(
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plat_dma_addr_to_phys(dev, dma_addr) >> PAGE_SHIFT);
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}
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/*
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* The affected CPUs below in 'cpu_needs_post_dma_flush()' can
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* speculatively fill random cachelines with stale data at any time,
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* requiring an extra flush post-DMA.
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*
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* Warning on the terminology - Linux calls an uncached area coherent;
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* MIPS terminology calls memory areas with hardware maintained coherency
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* coherent.
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*
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* Note that the R14000 and R16000 should also be checked for in this
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* condition. However this function is only called on non-I/O-coherent
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* systems and only the R10000 and R12000 are used in such systems, the
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* SGI IP28 Indigo² rsp. SGI IP32 aka O2.
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*/
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static inline bool cpu_needs_post_dma_flush(struct device *dev)
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{
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if (plat_device_is_coherent(dev))
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return false;
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switch (boot_cpu_type()) {
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case CPU_R10000:
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case CPU_R12000:
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case CPU_BMIPS5000:
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return true;
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default:
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/*
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* Presence of MAARs suggests that the CPU supports
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* speculatively prefetching data, and therefore requires
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* the post-DMA flush/invalidate.
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*/
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return cpu_has_maar;
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}
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}
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static gfp_t massage_gfp_flags(const struct device *dev, gfp_t gfp)
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{
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gfp_t dma_flag;
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#ifdef CONFIG_ISA
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if (dev == NULL)
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dma_flag = __GFP_DMA;
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else
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#endif
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#if defined(CONFIG_ZONE_DMA32) && defined(CONFIG_ZONE_DMA)
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if (dev == NULL || dev->coherent_dma_mask < DMA_BIT_MASK(32))
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dma_flag = __GFP_DMA;
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else if (dev->coherent_dma_mask < DMA_BIT_MASK(64))
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dma_flag = __GFP_DMA32;
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else
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#endif
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#if defined(CONFIG_ZONE_DMA32) && !defined(CONFIG_ZONE_DMA)
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if (dev == NULL || dev->coherent_dma_mask < DMA_BIT_MASK(64))
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dma_flag = __GFP_DMA32;
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else
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#endif
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#if defined(CONFIG_ZONE_DMA) && !defined(CONFIG_ZONE_DMA32)
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if (dev == NULL ||
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dev->coherent_dma_mask < DMA_BIT_MASK(sizeof(phys_addr_t) * 8))
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dma_flag = __GFP_DMA;
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else
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#endif
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dma_flag = 0;
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/* Don't invoke OOM killer */
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gfp |= __GFP_NORETRY;
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return gfp | dma_flag;
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}
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static void *mips_dma_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
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{
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void *ret;
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struct page *page = NULL;
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unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
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gfp = massage_gfp_flags(dev, gfp);
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if (IS_ENABLED(CONFIG_DMA_CMA) && gfpflags_allow_blocking(gfp))
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page = dma_alloc_from_contiguous(dev, count, get_order(size),
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gfp);
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if (!page)
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page = alloc_pages(gfp, get_order(size));
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if (!page)
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return NULL;
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ret = page_address(page);
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memset(ret, 0, size);
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*dma_handle = plat_map_dma_mem(dev, ret, size);
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if (!(attrs & DMA_ATTR_NON_CONSISTENT) &&
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!plat_device_is_coherent(dev)) {
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dma_cache_wback_inv((unsigned long) ret, size);
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ret = UNCAC_ADDR(ret);
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}
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return ret;
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}
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static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr,
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dma_addr_t dma_handle, unsigned long attrs)
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{
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unsigned long addr = (unsigned long) vaddr;
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unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
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struct page *page = NULL;
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plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL);
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if (!(attrs & DMA_ATTR_NON_CONSISTENT) && !plat_device_is_coherent(dev))
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addr = CAC_ADDR(addr);
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page = virt_to_page((void *) addr);
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if (!dma_release_from_contiguous(dev, page, count))
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__free_pages(page, get_order(size));
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}
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static int mips_dma_mmap(struct device *dev, struct vm_area_struct *vma,
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void *cpu_addr, dma_addr_t dma_addr, size_t size,
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unsigned long attrs)
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{
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unsigned long user_count = vma_pages(vma);
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unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
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unsigned long addr = (unsigned long)cpu_addr;
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unsigned long off = vma->vm_pgoff;
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unsigned long pfn;
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int ret = -ENXIO;
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if (!plat_device_is_coherent(dev))
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addr = CAC_ADDR(addr);
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pfn = page_to_pfn(virt_to_page((void *)addr));
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if (attrs & DMA_ATTR_WRITE_COMBINE)
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vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
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else
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vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
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if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret))
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return ret;
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if (off < count && user_count <= (count - off)) {
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ret = remap_pfn_range(vma, vma->vm_start,
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pfn + off,
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user_count << PAGE_SHIFT,
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vma->vm_page_prot);
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}
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return ret;
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}
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static inline void __dma_sync_virtual(void *addr, size_t size,
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enum dma_data_direction direction)
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{
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switch (direction) {
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case DMA_TO_DEVICE:
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dma_cache_wback((unsigned long)addr, size);
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break;
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case DMA_FROM_DEVICE:
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dma_cache_inv((unsigned long)addr, size);
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break;
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case DMA_BIDIRECTIONAL:
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dma_cache_wback_inv((unsigned long)addr, size);
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break;
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default:
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BUG();
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}
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}
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/*
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* A single sg entry may refer to multiple physically contiguous
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* pages. But we still need to process highmem pages individually.
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* If highmem is not configured then the bulk of this loop gets
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* optimized out.
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*/
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static inline void __dma_sync(struct page *page,
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unsigned long offset, size_t size, enum dma_data_direction direction)
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{
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size_t left = size;
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do {
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size_t len = left;
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if (PageHighMem(page)) {
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void *addr;
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if (offset + len > PAGE_SIZE) {
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if (offset >= PAGE_SIZE) {
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page += offset >> PAGE_SHIFT;
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offset &= ~PAGE_MASK;
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}
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len = PAGE_SIZE - offset;
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}
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addr = kmap_atomic(page);
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__dma_sync_virtual(addr + offset, len, direction);
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kunmap_atomic(addr);
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} else
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__dma_sync_virtual(page_address(page) + offset,
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size, direction);
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offset = 0;
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page++;
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left -= len;
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} while (left);
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}
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static void mips_dma_unmap_page(struct device *dev, dma_addr_t dma_addr,
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size_t size, enum dma_data_direction direction, unsigned long attrs)
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{
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if (cpu_needs_post_dma_flush(dev) && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
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__dma_sync(dma_addr_to_page(dev, dma_addr),
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dma_addr & ~PAGE_MASK, size, direction);
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plat_post_dma_flush(dev);
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plat_unmap_dma_mem(dev, dma_addr, size, direction);
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}
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static int mips_dma_map_sg(struct device *dev, struct scatterlist *sglist,
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int nents, enum dma_data_direction direction, unsigned long attrs)
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{
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int i;
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struct scatterlist *sg;
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for_each_sg(sglist, sg, nents, i) {
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if (!plat_device_is_coherent(dev) &&
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!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
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__dma_sync(sg_page(sg), sg->offset, sg->length,
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direction);
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#ifdef CONFIG_NEED_SG_DMA_LENGTH
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sg->dma_length = sg->length;
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#endif
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sg->dma_address = plat_map_dma_mem_page(dev, sg_page(sg)) +
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sg->offset;
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}
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return nents;
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}
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static dma_addr_t mips_dma_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size, enum dma_data_direction direction,
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unsigned long attrs)
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{
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if (!plat_device_is_coherent(dev) && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
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__dma_sync(page, offset, size, direction);
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return plat_map_dma_mem_page(dev, page) + offset;
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}
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static void mips_dma_unmap_sg(struct device *dev, struct scatterlist *sglist,
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int nhwentries, enum dma_data_direction direction,
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unsigned long attrs)
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{
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int i;
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struct scatterlist *sg;
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for_each_sg(sglist, sg, nhwentries, i) {
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if (!plat_device_is_coherent(dev) &&
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!(attrs & DMA_ATTR_SKIP_CPU_SYNC) &&
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direction != DMA_TO_DEVICE)
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__dma_sync(sg_page(sg), sg->offset, sg->length,
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direction);
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plat_unmap_dma_mem(dev, sg->dma_address, sg->length, direction);
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}
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}
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static void mips_dma_sync_single_for_cpu(struct device *dev,
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dma_addr_t dma_handle, size_t size, enum dma_data_direction direction)
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{
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if (cpu_needs_post_dma_flush(dev))
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__dma_sync(dma_addr_to_page(dev, dma_handle),
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dma_handle & ~PAGE_MASK, size, direction);
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plat_post_dma_flush(dev);
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}
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static void mips_dma_sync_single_for_device(struct device *dev,
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dma_addr_t dma_handle, size_t size, enum dma_data_direction direction)
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{
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if (!plat_device_is_coherent(dev))
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__dma_sync(dma_addr_to_page(dev, dma_handle),
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dma_handle & ~PAGE_MASK, size, direction);
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}
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static void mips_dma_sync_sg_for_cpu(struct device *dev,
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struct scatterlist *sglist, int nelems,
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enum dma_data_direction direction)
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{
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int i;
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struct scatterlist *sg;
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if (cpu_needs_post_dma_flush(dev)) {
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for_each_sg(sglist, sg, nelems, i) {
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__dma_sync(sg_page(sg), sg->offset, sg->length,
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direction);
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}
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}
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plat_post_dma_flush(dev);
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}
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static void mips_dma_sync_sg_for_device(struct device *dev,
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struct scatterlist *sglist, int nelems,
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enum dma_data_direction direction)
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{
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int i;
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struct scatterlist *sg;
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if (!plat_device_is_coherent(dev)) {
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for_each_sg(sglist, sg, nelems, i) {
|
|
__dma_sync(sg_page(sg), sg->offset, sg->length,
|
|
direction);
|
|
}
|
|
}
|
|
}
|
|
|
|
static int mips_dma_supported(struct device *dev, u64 mask)
|
|
{
|
|
return plat_dma_supported(dev, mask);
|
|
}
|
|
|
|
static void mips_dma_cache_sync(struct device *dev, void *vaddr, size_t size,
|
|
enum dma_data_direction direction)
|
|
{
|
|
BUG_ON(direction == DMA_NONE);
|
|
|
|
if (!plat_device_is_coherent(dev))
|
|
__dma_sync_virtual(vaddr, size, direction);
|
|
}
|
|
|
|
static const struct dma_map_ops mips_default_dma_map_ops = {
|
|
.alloc = mips_dma_alloc_coherent,
|
|
.free = mips_dma_free_coherent,
|
|
.mmap = mips_dma_mmap,
|
|
.map_page = mips_dma_map_page,
|
|
.unmap_page = mips_dma_unmap_page,
|
|
.map_sg = mips_dma_map_sg,
|
|
.unmap_sg = mips_dma_unmap_sg,
|
|
.sync_single_for_cpu = mips_dma_sync_single_for_cpu,
|
|
.sync_single_for_device = mips_dma_sync_single_for_device,
|
|
.sync_sg_for_cpu = mips_dma_sync_sg_for_cpu,
|
|
.sync_sg_for_device = mips_dma_sync_sg_for_device,
|
|
.dma_supported = mips_dma_supported,
|
|
.cache_sync = mips_dma_cache_sync,
|
|
};
|
|
|
|
const struct dma_map_ops *mips_dma_map_ops = &mips_default_dma_map_ops;
|
|
EXPORT_SYMBOL(mips_dma_map_ops);
|
|
|
|
#define PREALLOC_DMA_DEBUG_ENTRIES (1 << 16)
|
|
|
|
static int __init mips_dma_init(void)
|
|
{
|
|
dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
|
|
|
|
return 0;
|
|
}
|
|
fs_initcall(mips_dma_init);
|