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53b74ed2d0
This reverts commit5ddc7bd43c("mtd: atmel_nand: Support variable RB_EDGE interrupts") Because for current SoCs, the RB_EDGE3(i.e. bit 27) of HSMC_SR register does not exist, the RB_EDGE0 (i.e. bit 24) is the ready/busy line edge status bit. It is a datasheet bug. Cc: <stable@vger.kernel.org> Fixes: commit5ddc7bd43c("mtd: atmel_nand: Support variable RB_EDGE interrupts") Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
104 lines
3.5 KiB
C
104 lines
3.5 KiB
C
/*
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* Atmel Nand Flash Controller (NFC) - System peripherals regsters.
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* Based on SAMA5D3 datasheet.
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*
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* © Copyright 2013 Atmel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef ATMEL_NAND_NFC_H
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#define ATMEL_NAND_NFC_H
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/*
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* HSMC NFC registers
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*/
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#define ATMEL_HSMC_NFC_CFG 0x00 /* NFC Configuration Register */
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#define NFC_CFG_PAGESIZE (7 << 0)
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#define NFC_CFG_PAGESIZE_512 (0 << 0)
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#define NFC_CFG_PAGESIZE_1024 (1 << 0)
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#define NFC_CFG_PAGESIZE_2048 (2 << 0)
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#define NFC_CFG_PAGESIZE_4096 (3 << 0)
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#define NFC_CFG_PAGESIZE_8192 (4 << 0)
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#define NFC_CFG_WSPARE (1 << 8)
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#define NFC_CFG_RSPARE (1 << 9)
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#define NFC_CFG_NFC_DTOCYC (0xf << 16)
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#define NFC_CFG_NFC_DTOMUL (0x7 << 20)
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#define NFC_CFG_NFC_SPARESIZE (0x7f << 24)
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#define NFC_CFG_NFC_SPARESIZE_BIT_POS 24
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#define ATMEL_HSMC_NFC_CTRL 0x04 /* NFC Control Register */
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#define NFC_CTRL_ENABLE (1 << 0)
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#define NFC_CTRL_DISABLE (1 << 1)
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#define ATMEL_HSMC_NFC_SR 0x08 /* NFC Status Register */
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#define NFC_SR_BUSY (1 << 8)
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#define NFC_SR_XFR_DONE (1 << 16)
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#define NFC_SR_CMD_DONE (1 << 17)
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#define NFC_SR_DTOE (1 << 20)
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#define NFC_SR_UNDEF (1 << 21)
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#define NFC_SR_AWB (1 << 22)
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#define NFC_SR_ASE (1 << 23)
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#define NFC_SR_RB_EDGE (1 << 24)
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#define ATMEL_HSMC_NFC_IER 0x0c
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#define ATMEL_HSMC_NFC_IDR 0x10
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#define ATMEL_HSMC_NFC_IMR 0x14
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#define ATMEL_HSMC_NFC_CYCLE0 0x18 /* NFC Address Cycle Zero */
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#define ATMEL_HSMC_NFC_ADDR_CYCLE0 (0xff)
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#define ATMEL_HSMC_NFC_BANK 0x1c /* NFC Bank Register */
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#define ATMEL_HSMC_NFC_BANK0 (0 << 0)
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#define ATMEL_HSMC_NFC_BANK1 (1 << 0)
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#define nfc_writel(addr, reg, value) \
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writel((value), (addr) + ATMEL_HSMC_NFC_##reg)
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#define nfc_readl(addr, reg) \
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readl_relaxed((addr) + ATMEL_HSMC_NFC_##reg)
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/*
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* NFC Address Command definitions
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*/
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#define NFCADDR_CMD_CMD1 (0xff << 2) /* Command for Cycle 1 */
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#define NFCADDR_CMD_CMD1_BIT_POS 2
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#define NFCADDR_CMD_CMD2 (0xff << 10) /* Command for Cycle 2 */
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#define NFCADDR_CMD_CMD2_BIT_POS 10
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#define NFCADDR_CMD_VCMD2 (0x1 << 18) /* Valid Cycle 2 Command */
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#define NFCADDR_CMD_ACYCLE (0x7 << 19) /* Number of Address required */
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#define NFCADDR_CMD_ACYCLE_NONE (0x0 << 19)
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#define NFCADDR_CMD_ACYCLE_1 (0x1 << 19)
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#define NFCADDR_CMD_ACYCLE_2 (0x2 << 19)
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#define NFCADDR_CMD_ACYCLE_3 (0x3 << 19)
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#define NFCADDR_CMD_ACYCLE_4 (0x4 << 19)
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#define NFCADDR_CMD_ACYCLE_5 (0x5 << 19)
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#define NFCADDR_CMD_ACYCLE_BIT_POS 19
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#define NFCADDR_CMD_CSID (0x7 << 22) /* Chip Select Identifier */
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#define NFCADDR_CMD_CSID_0 (0x0 << 22)
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#define NFCADDR_CMD_CSID_1 (0x1 << 22)
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#define NFCADDR_CMD_CSID_2 (0x2 << 22)
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#define NFCADDR_CMD_CSID_3 (0x3 << 22)
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#define NFCADDR_CMD_CSID_4 (0x4 << 22)
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#define NFCADDR_CMD_CSID_5 (0x5 << 22)
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#define NFCADDR_CMD_CSID_6 (0x6 << 22)
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#define NFCADDR_CMD_CSID_7 (0x7 << 22)
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#define NFCADDR_CMD_DATAEN (0x1 << 25) /* Data Transfer Enable */
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#define NFCADDR_CMD_DATADIS (0x0 << 25) /* Data Transfer Disable */
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#define NFCADDR_CMD_NFCRD (0x0 << 26) /* NFC Read Enable */
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#define NFCADDR_CMD_NFCWR (0x1 << 26) /* NFC Write Enable */
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#define NFCADDR_CMD_NFCBUSY (0x1 << 27) /* NFC Busy */
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#define nfc_cmd_addr1234_writel(cmd, addr1234, nfc_base) \
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writel((addr1234), (cmd) + nfc_base)
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#define nfc_cmd_readl(bitstatus, nfc_base) \
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readl_relaxed((bitstatus) + nfc_base)
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#define NFC_TIME_OUT_MS 100
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#define NFC_SRAM_BANK1_OFFSET 0x1200
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#endif
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