YueHaibing 3d139703d3 fpga-manager: altera-ps-spi: Fix build error ...

If BITREVERSE is m and FPGA_MGR_ALTERA_PS_SPI is y,
build fails:

drivers/fpga/altera-ps-spi.o: In function `altera_ps_write':
altera-ps-spi.c:(.text+0x4ec): undefined reference to `byte_rev_table'

Select BITREVERSE to fix this.

Reported-by: Hulk Robot <hulkci@huawei.com>
Fixes: fcfe18f885f6 ("fpga-manager: altera-ps-spi: use bitrev8x4")
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Cc: stable <stable@vger.kernel.org>
Acked-by: Moritz Fischer <mdf@kernel.org>
Link: https://lore.kernel.org/r/20190708071356.50928-1-yuehaibing@huawei.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

2019-07-24 11:29:41 +02:00

..

altera-cvp.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 285

2019-06-05 17:36:37 +02:00

altera-fpga2sdram.c

…

altera-freeze-bridge.c

…

altera-hps2fpga.c

…

altera-pr-ip-core-plat.c

…

altera-pr-ip-core.c

…

altera-ps-spi.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 422

2019-06-05 17:37:15 +02:00

dfl-afu-dma-region.c

mm: add account_locked_vm utility function

2019-07-16 19:23:25 -07:00

dfl-afu-main.c

…

dfl-afu-region.c

…

dfl-afu.h

…

dfl-fme-br.c

…

dfl-fme-main.c

…

dfl-fme-mgr.c

fpga: dfl-fme-mgr: fix FME_PR_INTFC_ID register address.

2019-07-03 19:58:58 +02:00

dfl-fme-pr.c

fpga: dfl: fme: align PR buffer size per PR datawidth

2019-07-03 19:58:59 +02:00

dfl-fme-pr.h

…

dfl-fme-region.c

…

dfl-fme.h

…

dfl-pci.c

…

dfl.c

fpga: dfl: expand minor range when registering chrdev region

2019-05-24 20:32:12 +02:00

dfl.h

…

fpga-bridge.c

…

fpga-mgr.c

…

fpga-region.c

…

ice40-spi.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 441

2019-06-05 17:37:17 +02:00

Kconfig

fpga-manager: altera-ps-spi: Fix build error

2019-07-24 11:29:41 +02:00

machxo2-spi.c

…

Makefile

fpga manager: Adding FPGA Manager support for Xilinx zynqmp

2019-04-15 10:23:18 +02:00

of-fpga-region.c

drivers: Add generic helper to match by of_node

2019-06-24 05:22:31 +02:00

socfpga-a10.c

…

socfpga.c

…

stratix10-soc.c

fpga: stratix10-soc: fix use-after-free on s10_init()

2019-05-24 20:32:12 +02:00

ts73xx-fpga.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 285

2019-06-05 17:36:37 +02:00

xilinx-pr-decoupler.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 285

2019-06-05 17:36:37 +02:00

xilinx-spi.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 422

2019-06-05 17:37:15 +02:00

zynq-fpga.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 285

2019-06-05 17:36:37 +02:00

zynqmp-fpga.c

fpga: zynqmp-fpga: Correctly handle error pointer

2019-05-30 07:56:11 -07:00