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3b56496865
This adds the workaround for erratum 793 as a precaution in case not every BIOS implements it. This addresses CVE-2013-6885. Erratum text: [Revision Guide for AMD Family 16h Models 00h-0Fh Processors, document 51810 Rev. 3.04 November 2013] 793 Specific Combination of Writes to Write Combined Memory Types and Locked Instructions May Cause Core Hang Description Under a highly specific and detailed set of internal timing conditions, a locked instruction may trigger a timing sequence whereby the write to a write combined memory type is not flushed, causing the locked instruction to stall indefinitely. Potential Effect on System Processor core hang. Suggested Workaround BIOS should set MSR C001_1020[15] = 1b. Fix Planned No fix planned [ hpa: updated description, fixed typo in MSR name ] Signed-off-by: Borislav Petkov <bp@suse.de> Link: http://lkml.kernel.org/r/20140114230711.GS29865@pd.tnic Tested-by: Aravind Gopalakrishnan <aravind.gopalakrishnan@amd.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> |
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| mcheck | ||
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| amd.c | ||
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| bugs.c | ||
| centaur.c | ||
| common.c | ||
| cpu.h | ||
| cyrix.c | ||
| hypervisor.c | ||
| intel_cacheinfo.c | ||
| intel.c | ||
| Makefile | ||
| match.c | ||
| mkcapflags.sh | ||
| mshyperv.c | ||
| perf_event_amd_ibs.c | ||
| perf_event_amd_iommu.c | ||
| perf_event_amd_iommu.h | ||
| perf_event_amd_uncore.c | ||
| perf_event_amd.c | ||
| perf_event_intel_ds.c | ||
| perf_event_intel_lbr.c | ||
| perf_event_intel_uncore.c | ||
| perf_event_intel_uncore.h | ||
| perf_event_intel.c | ||
| perf_event_knc.c | ||
| perf_event_p4.c | ||
| perf_event_p6.c | ||
| perf_event.c | ||
| perf_event.h | ||
| perfctr-watchdog.c | ||
| powerflags.c | ||
| proc.c | ||
| rdrand.c | ||
| scattered.c | ||
| topology.c | ||
| transmeta.c | ||
| umc.c | ||
| vmware.c | ||