Leilk Liu adcbcfea15 spi: mediatek: fix spi clock usage error
spi clock manages flow:
  CLK_TOP_SYSPLL3_D2 ---> CLK_TOP_SPI_SEL ---> CLK_PERI_SPI0
     (source clock)           (clock mux)       (clock gate)
spi driver should choose source clock by clock mux, then enable
clock gate.

Signed-off-by: Leilk Liu <leilk.liu@mediatek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-08-31 15:26:50 +01:00
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