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The AT91 PLL rate configuration is done by configuring a multiplier/divider pair. The previous calculation was over-complicated (and apparently buggy). Simplify the implementation and add some comments to explain what is done here. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Reported-by: Gaël PORTAY <gael.portay@gmail.com> Tested-by: Gaël PORTAY <gael.portay@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> |
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.. | ||
clk-main.c | ||
clk-master.c | ||
clk-peripheral.c | ||
clk-pll.c | ||
clk-plldiv.c | ||
clk-programmable.c | ||
clk-slow.c | ||
clk-smd.c | ||
clk-system.c | ||
clk-usb.c | ||
clk-utmi.c | ||
Makefile | ||
pmc.c | ||
pmc.h | ||
sckc.c | ||
sckc.h |