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Siena has two problems with legacy interrupts: 1. There is no synchronisation between the ISR read completion, and the interrupt deassert message. 2. A downstream read at the "wrong" moment can return 0, and suppress generating the next interrupt. Falcon should suffer from both of these, and it appears it does. Enable EFX_WORKAROUND_15783 on Falcon as well. Also, when we see queues == 0, ensure we always schedule or rearm every event queue. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net> |
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.. | ||
bitfield.h | ||
efx.c | ||
efx.h | ||
enum.h | ||
ethtool.c | ||
falcon_boards.c | ||
falcon_gmac.c | ||
falcon_xmac.c | ||
falcon.c | ||
io.h | ||
Kconfig | ||
mac.h | ||
Makefile | ||
mcdi_mac.c | ||
mcdi_pcol.h | ||
mcdi_phy.c | ||
mcdi.c | ||
mcdi.h | ||
mdio_10g.c | ||
mdio_10g.h | ||
mtd.c | ||
net_driver.h | ||
nic.c | ||
nic.h | ||
phy.h | ||
qt202x_phy.c | ||
regs.h | ||
rx.c | ||
selftest.c | ||
selftest.h | ||
siena.c | ||
spi.h | ||
tenxpress.c | ||
tx.c | ||
workarounds.h |