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Setting the TI in MMUCR causes all the TLB bits in MMUCR to be cleared. Unfortunately, the TLB wired bits are also cleared when setting the TI bit, causing any wired TLB entries to become unwired. Use local_flush_tlb_all() which implements TLB flushing in a safer manner by using the memory-mapped TLB registers. As each CPU has its own PMB the modifications in pmb_init() only affect the local CPU, so only flush the local CPU's TLB. Signed-off-by: Matt Fleming <matt@console-pimps.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
150 lines
3.4 KiB
C
150 lines
3.4 KiB
C
/*
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* TLB flushing operations for SH with an MMU.
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*
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* Copyright (C) 1999 Niibe Yutaka
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* Copyright (C) 2003 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/mm.h>
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#include <asm/mmu_context.h>
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#include <asm/tlbflush.h>
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void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
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{
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unsigned int cpu = smp_processor_id();
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if (vma->vm_mm && cpu_context(cpu, vma->vm_mm) != NO_CONTEXT) {
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unsigned long flags;
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unsigned long asid;
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unsigned long saved_asid = MMU_NO_ASID;
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asid = cpu_asid(cpu, vma->vm_mm);
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page &= PAGE_MASK;
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local_irq_save(flags);
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if (vma->vm_mm != current->mm) {
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saved_asid = get_asid();
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set_asid(asid);
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}
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local_flush_tlb_one(asid, page);
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if (saved_asid != MMU_NO_ASID)
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set_asid(saved_asid);
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local_irq_restore(flags);
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}
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}
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void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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{
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struct mm_struct *mm = vma->vm_mm;
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unsigned int cpu = smp_processor_id();
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if (cpu_context(cpu, mm) != NO_CONTEXT) {
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unsigned long flags;
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int size;
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local_irq_save(flags);
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size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
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if (size > (MMU_NTLB_ENTRIES/4)) { /* Too many TLB to flush */
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cpu_context(cpu, mm) = NO_CONTEXT;
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if (mm == current->mm)
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activate_context(mm, cpu);
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} else {
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unsigned long asid;
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unsigned long saved_asid = MMU_NO_ASID;
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asid = cpu_asid(cpu, mm);
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start &= PAGE_MASK;
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end += (PAGE_SIZE - 1);
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end &= PAGE_MASK;
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if (mm != current->mm) {
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saved_asid = get_asid();
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set_asid(asid);
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}
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while (start < end) {
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local_flush_tlb_one(asid, start);
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start += PAGE_SIZE;
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}
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if (saved_asid != MMU_NO_ASID)
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set_asid(saved_asid);
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}
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local_irq_restore(flags);
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}
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}
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void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
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{
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unsigned int cpu = smp_processor_id();
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unsigned long flags;
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int size;
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local_irq_save(flags);
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size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
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if (size > (MMU_NTLB_ENTRIES/4)) { /* Too many TLB to flush */
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local_flush_tlb_all();
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} else {
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unsigned long asid;
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unsigned long saved_asid = get_asid();
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asid = cpu_asid(cpu, &init_mm);
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start &= PAGE_MASK;
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end += (PAGE_SIZE - 1);
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end &= PAGE_MASK;
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set_asid(asid);
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while (start < end) {
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local_flush_tlb_one(asid, start);
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start += PAGE_SIZE;
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}
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set_asid(saved_asid);
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}
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local_irq_restore(flags);
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}
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void local_flush_tlb_mm(struct mm_struct *mm)
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{
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unsigned int cpu = smp_processor_id();
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/* Invalidate all TLB of this process. */
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/* Instead of invalidating each TLB, we get new MMU context. */
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if (cpu_context(cpu, mm) != NO_CONTEXT) {
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unsigned long flags;
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local_irq_save(flags);
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cpu_context(cpu, mm) = NO_CONTEXT;
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if (mm == current->mm)
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activate_context(mm, cpu);
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local_irq_restore(flags);
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}
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}
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void local_flush_tlb_all(void)
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{
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unsigned long flags, status;
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int i;
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/*
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* Flush all the TLB.
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*/
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local_irq_save(flags);
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jump_to_uncached();
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status = __raw_readl(MMUCR);
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status = ((status & MMUCR_URB) >> MMUCR_URB_SHIFT);
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if (status == 0)
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status = MMUCR_URB_NENTRIES;
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for (i = 0; i < status; i++)
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__raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8));
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for (i = 0; i < 4; i++)
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__raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8));
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back_to_cached();
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ctrl_barrier();
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local_irq_restore(flags);
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}
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