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8e267f3da5
Everything required to populate NVIDIA Tegra devices from the device tree. This patch adds a new DT_MACHINE_DESC() which matches against a tegra20 device tree. So far it only registers the on-chip devices, but it will be refined in follow on patches to configure clocks and pin IO from the device tree also. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
140 lines
2.6 KiB
Plaintext
140 lines
2.6 KiB
Plaintext
/include/ "skeleton.dtsi"
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/ {
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compatible = "nvidia,tegra20";
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interrupt-parent = <&intc>;
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intc: interrupt-controller@50041000 {
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compatible = "nvidia,tegra20-gic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = < 0x50041000 0x1000 >,
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< 0x50040100 0x0100 >;
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};
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i2c@7000c000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra20-i2c";
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reg = <0x7000C000 0x100>;
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interrupts = < 70 >;
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};
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i2c@7000c400 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra20-i2c";
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reg = <0x7000C400 0x100>;
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interrupts = < 116 >;
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};
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i2c@7000c500 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra20-i2c";
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reg = <0x7000C500 0x100>;
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interrupts = < 124 >;
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};
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i2c@7000d000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra20-i2c";
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reg = <0x7000D000 0x200>;
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interrupts = < 85 >;
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};
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i2s@70002800 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra20-i2s";
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reg = <0x70002800 0x200>;
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interrupts = < 45 >;
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dma-channel = < 2 >;
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};
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i2s@70002a00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra20-i2s";
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reg = <0x70002a00 0x200>;
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interrupts = < 35 >;
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dma-channel = < 1 >;
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};
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das@70000c00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra20-das";
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reg = <0x70000c00 0x80>;
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};
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gpio: gpio@6000d000 {
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compatible = "nvidia,tegra20-gpio";
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reg = < 0x6000d000 0x1000 >;
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interrupts = < 64 65 66 67 87 119 121 >;
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#gpio-cells = <2>;
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gpio-controller;
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};
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serial@70006000 {
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compatible = "nvidia,tegra20-uart";
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reg = <0x70006000 0x40>;
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reg-shift = <2>;
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interrupts = < 68 >;
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};
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serial@70006040 {
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compatible = "nvidia,tegra20-uart";
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reg = <0x70006040 0x40>;
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reg-shift = <2>;
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interrupts = < 69 >;
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};
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serial@70006200 {
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compatible = "nvidia,tegra20-uart";
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reg = <0x70006200 0x100>;
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reg-shift = <2>;
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interrupts = < 78 >;
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};
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serial@70006300 {
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compatible = "nvidia,tegra20-uart";
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reg = <0x70006300 0x100>;
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reg-shift = <2>;
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interrupts = < 122 >;
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};
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serial@70006400 {
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compatible = "nvidia,tegra20-uart";
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reg = <0x70006400 0x100>;
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reg-shift = <2>;
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interrupts = < 123 >;
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};
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sdhci@c8000000 {
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compatible = "nvidia,tegra20-sdhci";
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reg = <0xc8000000 0x200>;
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interrupts = < 46 >;
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};
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sdhci@c8000200 {
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compatible = "nvidia,tegra20-sdhci";
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reg = <0xc8000200 0x200>;
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interrupts = < 47 >;
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};
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sdhci@c8000400 {
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compatible = "nvidia,tegra20-sdhci";
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reg = <0xc8000400 0x200>;
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interrupts = < 51 >;
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};
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sdhci@c8000600 {
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compatible = "nvidia,tegra20-sdhci";
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reg = <0xc8000600 0x200>;
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interrupts = < 63 >;
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};
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};
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