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39f0fb6a34
The older simple ColdFire interrupt controller has no one-to-one mapping of interrupt numbers to bits in the interrupt mask register. Create a mapping array that each ColdFire CPU type can populate with its available interrupts and the bits that each use in the interrupt mask register. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
116 lines
3.0 KiB
C
116 lines
3.0 KiB
C
/***************************************************************************/
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/*
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* linux/arch/m68knommu/platform/5249/config.c
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*
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* Copyright (C) 2002, Greg Ungerer (gerg@snapgear.com)
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*/
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/***************************************************************************/
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#include <linux/kernel.h>
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#include <linux/param.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <asm/machdep.h>
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#include <asm/coldfire.h>
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#include <asm/mcfsim.h>
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#include <asm/mcfuart.h>
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/***************************************************************************/
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static struct mcf_platform_uart m5249_uart_platform[] = {
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{
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.mapbase = MCF_MBAR + MCFUART_BASE1,
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.irq = 73,
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},
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{
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.mapbase = MCF_MBAR + MCFUART_BASE2,
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.irq = 74,
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},
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{ },
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};
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static struct platform_device m5249_uart = {
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.name = "mcfuart",
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.id = 0,
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.dev.platform_data = m5249_uart_platform,
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};
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static struct platform_device *m5249_devices[] __initdata = {
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&m5249_uart,
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};
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/***************************************************************************/
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static void __init m5249_uart_init_line(int line, int irq)
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{
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if (line == 0) {
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writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
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writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
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mcf_mapirq2imr(irq, MCFINTC_UART0);
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} else if (line == 1) {
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writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
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writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
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mcf_mapirq2imr(irq, MCFINTC_UART1);
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}
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}
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static void __init m5249_uarts_init(void)
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{
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const int nrlines = ARRAY_SIZE(m5249_uart_platform);
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int line;
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for (line = 0; (line < nrlines); line++)
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m5249_uart_init_line(line, m5249_uart_platform[line].irq);
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}
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/***************************************************************************/
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static void __init m5249_timers_init(void)
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{
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/* Timer1 is always used as system timer */
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writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
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MCF_MBAR + MCFSIM_TIMER1ICR);
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mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
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#ifdef CONFIG_HIGHPROFILE
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/* Timer2 is to be used as a high speed profile timer */
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writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
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MCF_MBAR + MCFSIM_TIMER2ICR);
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mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
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#endif
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}
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/***************************************************************************/
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void m5249_cpu_reset(void)
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{
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local_irq_disable();
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/* Set watchdog to soft reset, and enabled */
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__raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
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for (;;)
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/* wait for watchdog to timeout */;
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}
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/***************************************************************************/
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void __init config_BSP(char *commandp, int size)
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{
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mach_reset = m5249_cpu_reset;
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m5249_timers_init();
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m5249_uarts_init();
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}
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/***************************************************************************/
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static int __init init_BSP(void)
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{
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platform_add_devices(m5249_devices, ARRAY_SIZE(m5249_devices));
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return 0;
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}
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arch_initcall(init_BSP);
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/***************************************************************************/
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