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
This processor only have one FEC and its MDIO pins are located at a different offset than the code used for the current CONFIG_M527x. Tesed on M5271EVB eval platform. Without this patch the FEC driver will report no PHY attached if the bootloader does not pre-initialize the PAR_FECI2C GPIO register. Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>