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a07187c992
For Intel Haswell/Broadwell display HD-A controller, the 24MHz HD-A link BCLK is converted from Core Display Clock (CDCLK): BCLK = CDCLK * M / N And there are two registers EM4 and EM5 to program M, N value respectively. The EM4/EM5 values will be lost and when the display power well is disabled. BIOS programs CDCLK selected by OEM and EM4/EM5, but BIOS has no idea about display power well on/off at runtime. So the M/N can be wrong if non-default CDCLK is used when the audio controller resumes, which results in an invalid BCLK and abnormal audio playback rate. So this patch saves and restores valid M/N values on controller suspend/resume. And 'struct hda_intel' is defined to contain standard HD-A 'struct azx' and Intel specific fields, as Takashi suggested. Signed-off-by: Mengdong Lin <mengdong.lin@intel.com> Cc: <stable@vger.kernel.org> Signed-off-by: Takashi Iwai <tiwai@suse.de> |
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| .. | ||
| ca0132_regs.h | ||
| hda_auto_parser.c | ||
| hda_auto_parser.h | ||
| hda_beep.c | ||
| hda_beep.h | ||
| hda_codec.c | ||
| hda_codec.h | ||
| hda_controller.c | ||
| hda_controller.h | ||
| hda_eld.c | ||
| hda_generic.c | ||
| hda_generic.h | ||
| hda_hwdep.c | ||
| hda_i915.c | ||
| hda_i915.h | ||
| hda_intel_trace.h | ||
| hda_intel.c | ||
| hda_jack.c | ||
| hda_jack.h | ||
| hda_local.h | ||
| hda_priv.h | ||
| hda_proc.c | ||
| hda_sysfs.c | ||
| hda_tegra.c | ||
| hda_trace.h | ||
| Kconfig | ||
| Makefile | ||
| patch_analog.c | ||
| patch_ca0110.c | ||
| patch_ca0132.c | ||
| patch_cirrus.c | ||
| patch_cmedia.c | ||
| patch_conexant.c | ||
| patch_hdmi.c | ||
| patch_realtek.c | ||
| patch_si3054.c | ||
| patch_sigmatel.c | ||
| patch_via.c | ||
| thinkpad_helper.c | ||