Shobhit Kumar 4ba7d93afe drm/i915: Correct the base value while updating LP_OUTPUT_HOLD in MIPI_PORT_CTRL ... LP_OUTPUT_HOLD is only in MIPI_PORT_CTRL(PORT_A) even for PORT_C in case of dual link. In the dual link implementation, the bit is correctly set or unset for hardcoded PORT_A, but for bit update the register base value is read by using MIPI_PORT_CTRL(port) in a loop. The second iteration will read base value from PORT_C and program for PORT_A. Mostly in case of dual link all other bit values should be same, but logically we should read from PORT_A. So hardcode to read initial value from PORT_A as well. Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com>		2015-02-09 20:21:08 +02:00
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drm	drm/i915: Correct the base value while updating LP_OUTPUT_HOLD in MIPI_PORT_CTRL	2015-02-09 20:21:08 +02:00
host1x	gpu: host1x: mipi: Set MIPI_CAL_BIAS_PAD_CFG1 register	2014-11-13 16:11:57 +01:00
ipu-v3	gpu: ipu-di: Switch to DIV_ROUND_CLOSEST for DI clock divider calc	2015-01-07 19:15:04 +01:00
vga	Merge branch 'sched-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip	2014-10-13 16:23:15 +02:00
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