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0f75a96bc0
Add support for MFC device to plat-s5p, mach-exynos4, mach-s5pv210: - clock support - memory mapping and reserving - s5p_device_mfc platform device Signed-off-by: Kamil Debski <k.debski@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
124 lines
3.0 KiB
C
124 lines
3.0 KiB
C
/* linux/arch/arm/plat-s5p/dev-mfc.c
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*
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* Copyright (C) 2010-2011 Samsung Electronics Co.Ltd
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*
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* Base S5P MFC resource and device definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/memblock.h>
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#include <linux/ioport.h>
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#include <mach/map.h>
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#include <plat/devs.h>
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#include <plat/irqs.h>
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#include <plat/mfc.h>
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static struct resource s5p_mfc_resource[] = {
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[0] = {
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.start = S5P_PA_MFC,
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.end = S5P_PA_MFC + SZ_64K - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_MFC,
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.end = IRQ_MFC,
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.flags = IORESOURCE_IRQ,
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}
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};
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struct platform_device s5p_device_mfc = {
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.name = "s5p-mfc",
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.id = -1,
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.num_resources = ARRAY_SIZE(s5p_mfc_resource),
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.resource = s5p_mfc_resource,
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};
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/*
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* MFC hardware has 2 memory interfaces which are modelled as two separate
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* platform devices to let dma-mapping distinguish between them.
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*
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* MFC parent device (s5p_device_mfc) must be registered before memory
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* interface specific devices (s5p_device_mfc_l and s5p_device_mfc_r).
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*/
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static u64 s5p_mfc_dma_mask = DMA_BIT_MASK(32);
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struct platform_device s5p_device_mfc_l = {
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.name = "s5p-mfc-l",
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.id = -1,
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.dev = {
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.parent = &s5p_device_mfc.dev,
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.dma_mask = &s5p_mfc_dma_mask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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};
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struct platform_device s5p_device_mfc_r = {
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.name = "s5p-mfc-r",
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.id = -1,
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.dev = {
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.parent = &s5p_device_mfc.dev,
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.dma_mask = &s5p_mfc_dma_mask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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};
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struct s5p_mfc_reserved_mem {
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phys_addr_t base;
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unsigned long size;
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struct device *dev;
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};
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static struct s5p_mfc_reserved_mem s5p_mfc_mem[2] __initdata;
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void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
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phys_addr_t lbase, unsigned int lsize)
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{
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int i;
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s5p_mfc_mem[0].dev = &s5p_device_mfc_r.dev;
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s5p_mfc_mem[0].base = rbase;
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s5p_mfc_mem[0].size = rsize;
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s5p_mfc_mem[1].dev = &s5p_device_mfc_l.dev;
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s5p_mfc_mem[1].base = lbase;
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s5p_mfc_mem[1].size = lsize;
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for (i = 0; i < ARRAY_SIZE(s5p_mfc_mem); i++) {
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struct s5p_mfc_reserved_mem *area = &s5p_mfc_mem[i];
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if (memblock_remove(area->base, area->size)) {
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printk(KERN_ERR "Failed to reserve memory for MFC device (%ld bytes at 0x%08lx)\n",
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area->size, (unsigned long) area->base);
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area->base = 0;
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}
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}
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}
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static int __init s5p_mfc_memory_init(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(s5p_mfc_mem); i++) {
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struct s5p_mfc_reserved_mem *area = &s5p_mfc_mem[i];
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if (!area->base)
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continue;
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if (dma_declare_coherent_memory(area->dev, area->base,
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area->base, area->size,
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DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0)
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printk(KERN_ERR "Failed to declare coherent memory for MFC device (%ld bytes at 0x%08lx)\n",
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area->size, (unsigned long) area->base);
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}
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return 0;
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}
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device_initcall(s5p_mfc_memory_init);
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