Zhenyu Wang 4bfe6b6876 drm/i915: Fix and cleanup DPLL calculation for Ironlake ...

When the ideal error range can't be reached, this will safely use
a most closed one. Clean up some dumb codes in DPLL function too.

This fixes DPLL clock issue against one monitor at 1680x1050@60hz.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>

2009-11-05 14:00:32 -08:00

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drm

drm/i915: Fix and cleanup DPLL calculation for Ironlake

2009-11-05 14:00:32 -08:00

vga

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Makefile

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