mirror of
https://github.com/FEX-Emu/linux.git
synced 2024-12-21 08:53:41 +00:00
06cfa55694
Move register and other definitions out of the include/asm-arm/arch-s3c2410 into the the arch directories of include/asm-arm/plat-s3c24xx and include/asm-arm/plat-s3c. This move is in preperation of the merging of s3c2400 and s3c6400. The following git mv commands are needed before this patch can be applied: git mv include/asm-arm/arch-s3c2410/regs-ac97.h include/asm-arm/plat-s3c/regs-ac97.h git mv include/asm-arm/arch-s3c2410/regs-adc.h include/asm-arm/plat-s3c/regs-adc.h git mv include/asm-arm/arch-s3c2410/regs-iis.h include/asm-arm/plat-s3c24xx/regs-iis.h git mv include/asm-arm/arch-s3c2410/regs-spi.h include/asm-arm/plat-s3c24xx/regs-spi.h git mv include/asm-arm/arch-s3c2410/regs-udc.h include/asm-arm/plat-s3c24xx/regs-udc.h git mv include/asm-arm/arch-s3c2410/udc.h include/asm-arm/plat-s3c24xx/udc.h Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
61 lines
1.8 KiB
C
61 lines
1.8 KiB
C
/* linux/include/asm-arm/arch-s3c2410/regs-adc.h
|
|
*
|
|
* Copyright (c) 2004 Shannon Holland <holland@loser.net>
|
|
*
|
|
* This program is free software; yosu can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*
|
|
* S3C2410 ADC registers
|
|
*/
|
|
|
|
#ifndef __ASM_ARCH_REGS_ADC_H
|
|
#define __ASM_ARCH_REGS_ADC_H "regs-adc.h"
|
|
|
|
#define S3C2410_ADCREG(x) (x)
|
|
|
|
#define S3C2410_ADCCON S3C2410_ADCREG(0x00)
|
|
#define S3C2410_ADCTSC S3C2410_ADCREG(0x04)
|
|
#define S3C2410_ADCDLY S3C2410_ADCREG(0x08)
|
|
#define S3C2410_ADCDAT0 S3C2410_ADCREG(0x0C)
|
|
#define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10)
|
|
|
|
|
|
/* ADCCON Register Bits */
|
|
#define S3C2410_ADCCON_ECFLG (1<<15)
|
|
#define S3C2410_ADCCON_PRSCEN (1<<14)
|
|
#define S3C2410_ADCCON_PRSCVL(x) (((x)&0xFF)<<6)
|
|
#define S3C2410_ADCCON_PRSCVLMASK (0xFF<<6)
|
|
#define S3C2410_ADCCON_SELMUX(x) (((x)&0x7)<<3)
|
|
#define S3C2410_ADCCON_MUXMASK (0x7<<3)
|
|
#define S3C2410_ADCCON_STDBM (1<<2)
|
|
#define S3C2410_ADCCON_READ_START (1<<1)
|
|
#define S3C2410_ADCCON_ENABLE_START (1<<0)
|
|
#define S3C2410_ADCCON_STARTMASK (0x3<<0)
|
|
|
|
|
|
/* ADCTSC Register Bits */
|
|
#define S3C2410_ADCTSC_YM_SEN (1<<7)
|
|
#define S3C2410_ADCTSC_YP_SEN (1<<6)
|
|
#define S3C2410_ADCTSC_XM_SEN (1<<5)
|
|
#define S3C2410_ADCTSC_XP_SEN (1<<4)
|
|
#define S3C2410_ADCTSC_PULL_UP_DISABLE (1<<3)
|
|
#define S3C2410_ADCTSC_AUTO_PST (1<<2)
|
|
#define S3C2410_ADCTSC_XY_PST(x) (((x)&0x3)<<0)
|
|
|
|
/* ADCDAT0 Bits */
|
|
#define S3C2410_ADCDAT0_UPDOWN (1<<15)
|
|
#define S3C2410_ADCDAT0_AUTO_PST (1<<14)
|
|
#define S3C2410_ADCDAT0_XY_PST (0x3<<12)
|
|
#define S3C2410_ADCDAT0_XPDATA_MASK (0x03FF)
|
|
|
|
/* ADCDAT1 Bits */
|
|
#define S3C2410_ADCDAT1_UPDOWN (1<<15)
|
|
#define S3C2410_ADCDAT1_AUTO_PST (1<<14)
|
|
#define S3C2410_ADCDAT1_XY_PST (0x3<<12)
|
|
#define S3C2410_ADCDAT1_YPDATA_MASK (0x03FF)
|
|
|
|
#endif /* __ASM_ARCH_REGS_ADC_H */
|
|
|
|
|