John David Anglin 5035b230e7 parisc: Also flush data TLB in flush_icache_page_asm ... This is the second issue I noticed in reviewing the parisc TLB code. The fic instruction may use either the instruction or data TLB in flushing the instruction cache. Thus, on machines with a split TLB, we should also flush the data TLB after setting up the temporary alias registers. Although this has no functional impact, I changed the pdtlb and pitlb instructions to consistently use the index register %r0. These instructions do not support integer displacements. Tested on rp3440 and c8000. Signed-off-by: John David Anglin <dave.anglin@bell.net> Cc: <stable@vger.kernel.org> # v3.16+ Signed-off-by: Helge Deller <deller@gmx.de>		2016-11-25 12:32:01 +01:00
..
configs	mm/usercopy: get rid of CONFIG_DEBUG_STRICT_USER_COPY_CHECKS	2016-08-30 10:10:21 -07:00
include	parisc: Ignore the pkey system calls for now	2016-11-02 23:07:14 +01:00
kernel	parisc: Also flush data TLB in flush_icache_page_asm	2016-11-25 12:32:01 +01:00
lib	parisc: Add hardened usercopy feature	2016-10-06 22:10:19 +02:00
math-emu	parisc: Fix typo in fpudispatch.c	2016-05-22 22:29:07 +02:00
mm	parisc: Show trap name in kernel crash	2016-10-11 20:52:47 +02:00
oprofile
defpalo.conf
install.sh
Kconfig	parisc: Switch to generic sched_clock implementation	2016-11-25 12:31:58 +01:00
Kconfig.debug	parisc: Fix ftrace function tracer	2016-04-14 17:47:19 +02:00
Makefile	parisc: Fix ftrace function tracer	2016-04-14 17:47:19 +02:00
nm