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576132b426
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
292 lines
8.3 KiB
C
292 lines
8.3 KiB
C
/* irq-routing.c: IRQ routing
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*
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* Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/sched.h>
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#include <linux/random.h>
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#include <linux/init.h>
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#include <linux/serial_reg.h>
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#include <asm/io.h>
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#include <asm/irq-routing.h>
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#include <asm/irc-regs.h>
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#include <asm/serial-regs.h>
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#include <asm/dma.h>
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struct irq_level frv_irq_levels[16] = {
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[0 ... 15] = {
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.lock = SPIN_LOCK_UNLOCKED,
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}
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};
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struct irq_group *irq_groups[NR_IRQ_GROUPS];
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extern struct irq_group frv_cpu_irqs;
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void __init frv_irq_route(struct irq_source *source, int irqlevel)
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{
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source->level = &frv_irq_levels[irqlevel];
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source->next = frv_irq_levels[irqlevel].sources;
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frv_irq_levels[irqlevel].sources = source;
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}
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void __init frv_irq_route_external(struct irq_source *source, int irq)
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{
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int irqlevel = 0;
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switch (irq) {
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case IRQ_CPU_EXTERNAL0: irqlevel = IRQ_XIRQ0_LEVEL; break;
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case IRQ_CPU_EXTERNAL1: irqlevel = IRQ_XIRQ1_LEVEL; break;
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case IRQ_CPU_EXTERNAL2: irqlevel = IRQ_XIRQ2_LEVEL; break;
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case IRQ_CPU_EXTERNAL3: irqlevel = IRQ_XIRQ3_LEVEL; break;
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case IRQ_CPU_EXTERNAL4: irqlevel = IRQ_XIRQ4_LEVEL; break;
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case IRQ_CPU_EXTERNAL5: irqlevel = IRQ_XIRQ5_LEVEL; break;
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case IRQ_CPU_EXTERNAL6: irqlevel = IRQ_XIRQ6_LEVEL; break;
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case IRQ_CPU_EXTERNAL7: irqlevel = IRQ_XIRQ7_LEVEL; break;
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default: BUG();
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}
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source->level = &frv_irq_levels[irqlevel];
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source->next = frv_irq_levels[irqlevel].sources;
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frv_irq_levels[irqlevel].sources = source;
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}
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void __init frv_irq_set_group(struct irq_group *group)
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{
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irq_groups[group->first_irq >> NR_IRQ_LOG2_ACTIONS_PER_GROUP] = group;
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}
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void distribute_irqs(struct irq_group *group, unsigned long irqmask)
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{
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struct irqaction *action;
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int irq;
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while (irqmask) {
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asm("scan %1,gr0,%0" : "=r"(irq) : "r"(irqmask));
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if (irq < 0 || irq > 31)
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asm volatile("break");
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irq = 31 - irq;
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irqmask &= ~(1 << irq);
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action = group->actions[irq];
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irq += group->first_irq;
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if (action) {
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int status = 0;
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// if (!(action->flags & SA_INTERRUPT))
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// local_irq_enable();
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do {
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status |= action->flags;
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action->handler(irq, action->dev_id, __frame);
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action = action->next;
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} while (action);
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if (status & SA_SAMPLE_RANDOM)
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add_interrupt_randomness(irq);
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local_irq_disable();
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}
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}
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}
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/*****************************************************************************/
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/*
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* CPU UART interrupts
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*/
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static void frv_cpuuart_doirq(struct irq_source *source)
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{
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// uint8_t iir = readb(source->muxdata + UART_IIR * 8);
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// if ((iir & 0x0f) != UART_IIR_NO_INT)
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distribute_irqs(&frv_cpu_irqs, source->irqmask);
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}
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struct irq_source frv_cpuuart[2] = {
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#define __CPUUART(X, A) \
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[X] = { \
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.muxname = "uart", \
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.muxdata = (volatile void __iomem *)(unsigned long)A,\
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.irqmask = 1 << IRQ_CPU_UART##X, \
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.doirq = frv_cpuuart_doirq, \
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}
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__CPUUART(0, UART0_BASE),
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__CPUUART(1, UART1_BASE),
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};
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/*****************************************************************************/
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/*
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* CPU DMA interrupts
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*/
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static void frv_cpudma_doirq(struct irq_source *source)
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{
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uint32_t cstr = readl(source->muxdata + DMAC_CSTRx);
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if (cstr & DMAC_CSTRx_INT)
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distribute_irqs(&frv_cpu_irqs, source->irqmask);
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}
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struct irq_source frv_cpudma[8] = {
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#define __CPUDMA(X, A) \
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[X] = { \
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.muxname = "dma", \
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.muxdata = (volatile void __iomem *)(unsigned long)A,\
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.irqmask = 1 << IRQ_CPU_DMA##X, \
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.doirq = frv_cpudma_doirq, \
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}
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__CPUDMA(0, 0xfe000900),
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__CPUDMA(1, 0xfe000980),
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__CPUDMA(2, 0xfe000a00),
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__CPUDMA(3, 0xfe000a80),
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__CPUDMA(4, 0xfe001000),
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__CPUDMA(5, 0xfe001080),
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__CPUDMA(6, 0xfe001100),
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__CPUDMA(7, 0xfe001180),
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};
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/*****************************************************************************/
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/*
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* CPU timer interrupts - can't tell whether they've generated an interrupt or not
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*/
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static void frv_cputimer_doirq(struct irq_source *source)
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{
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distribute_irqs(&frv_cpu_irqs, source->irqmask);
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}
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struct irq_source frv_cputimer[3] = {
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#define __CPUTIMER(X) \
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[X] = { \
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.muxname = "timer", \
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.muxdata = NULL, \
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.irqmask = 1 << IRQ_CPU_TIMER##X, \
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.doirq = frv_cputimer_doirq, \
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}
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__CPUTIMER(0),
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__CPUTIMER(1),
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__CPUTIMER(2),
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};
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/*****************************************************************************/
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/*
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* external CPU interrupts - can't tell directly whether they've generated an interrupt or not
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*/
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static void frv_cpuexternal_doirq(struct irq_source *source)
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{
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distribute_irqs(&frv_cpu_irqs, source->irqmask);
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}
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struct irq_source frv_cpuexternal[8] = {
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#define __CPUEXTERNAL(X) \
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[X] = { \
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.muxname = "ext", \
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.muxdata = NULL, \
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.irqmask = 1 << IRQ_CPU_EXTERNAL##X, \
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.doirq = frv_cpuexternal_doirq, \
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}
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__CPUEXTERNAL(0),
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__CPUEXTERNAL(1),
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__CPUEXTERNAL(2),
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__CPUEXTERNAL(3),
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__CPUEXTERNAL(4),
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__CPUEXTERNAL(5),
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__CPUEXTERNAL(6),
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__CPUEXTERNAL(7),
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};
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#define set_IRR(N,A,B,C,D) __set_IRR(N, (A << 28) | (B << 24) | (C << 20) | (D << 16))
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struct irq_group frv_cpu_irqs = {
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.sources = {
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[IRQ_CPU_UART0] = &frv_cpuuart[0],
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[IRQ_CPU_UART1] = &frv_cpuuart[1],
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[IRQ_CPU_TIMER0] = &frv_cputimer[0],
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[IRQ_CPU_TIMER1] = &frv_cputimer[1],
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[IRQ_CPU_TIMER2] = &frv_cputimer[2],
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[IRQ_CPU_DMA0] = &frv_cpudma[0],
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[IRQ_CPU_DMA1] = &frv_cpudma[1],
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[IRQ_CPU_DMA2] = &frv_cpudma[2],
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[IRQ_CPU_DMA3] = &frv_cpudma[3],
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[IRQ_CPU_DMA4] = &frv_cpudma[4],
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[IRQ_CPU_DMA5] = &frv_cpudma[5],
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[IRQ_CPU_DMA6] = &frv_cpudma[6],
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[IRQ_CPU_DMA7] = &frv_cpudma[7],
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[IRQ_CPU_EXTERNAL0] = &frv_cpuexternal[0],
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[IRQ_CPU_EXTERNAL1] = &frv_cpuexternal[1],
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[IRQ_CPU_EXTERNAL2] = &frv_cpuexternal[2],
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[IRQ_CPU_EXTERNAL3] = &frv_cpuexternal[3],
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[IRQ_CPU_EXTERNAL4] = &frv_cpuexternal[4],
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[IRQ_CPU_EXTERNAL5] = &frv_cpuexternal[5],
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[IRQ_CPU_EXTERNAL6] = &frv_cpuexternal[6],
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[IRQ_CPU_EXTERNAL7] = &frv_cpuexternal[7],
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},
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};
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/*****************************************************************************/
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/*
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* route the CPU's interrupt sources
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*/
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void __init route_cpu_irqs(void)
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{
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frv_irq_set_group(&frv_cpu_irqs);
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__set_IITMR(0, 0x003f0000); /* DMA0-3, TIMER0-2 IRQ detect levels */
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__set_IITMR(1, 0x20000000); /* ERR0-1, UART0-1, DMA4-7 IRQ detect levels */
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/* route UART and error interrupts */
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frv_irq_route(&frv_cpuuart[0], IRQ_UART0_LEVEL);
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frv_irq_route(&frv_cpuuart[1], IRQ_UART1_LEVEL);
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set_IRR(6, IRQ_GDBSTUB_LEVEL, IRQ_GDBSTUB_LEVEL, IRQ_UART1_LEVEL, IRQ_UART0_LEVEL);
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/* route DMA channel interrupts */
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frv_irq_route(&frv_cpudma[0], IRQ_DMA0_LEVEL);
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frv_irq_route(&frv_cpudma[1], IRQ_DMA1_LEVEL);
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frv_irq_route(&frv_cpudma[2], IRQ_DMA2_LEVEL);
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frv_irq_route(&frv_cpudma[3], IRQ_DMA3_LEVEL);
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frv_irq_route(&frv_cpudma[4], IRQ_DMA4_LEVEL);
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frv_irq_route(&frv_cpudma[5], IRQ_DMA5_LEVEL);
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frv_irq_route(&frv_cpudma[6], IRQ_DMA6_LEVEL);
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frv_irq_route(&frv_cpudma[7], IRQ_DMA7_LEVEL);
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set_IRR(4, IRQ_DMA3_LEVEL, IRQ_DMA2_LEVEL, IRQ_DMA1_LEVEL, IRQ_DMA0_LEVEL);
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set_IRR(7, IRQ_DMA7_LEVEL, IRQ_DMA6_LEVEL, IRQ_DMA5_LEVEL, IRQ_DMA4_LEVEL);
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/* route timer interrupts */
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frv_irq_route(&frv_cputimer[0], IRQ_TIMER0_LEVEL);
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frv_irq_route(&frv_cputimer[1], IRQ_TIMER1_LEVEL);
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frv_irq_route(&frv_cputimer[2], IRQ_TIMER2_LEVEL);
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set_IRR(5, 0, IRQ_TIMER2_LEVEL, IRQ_TIMER1_LEVEL, IRQ_TIMER0_LEVEL);
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/* route external interrupts */
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frv_irq_route(&frv_cpuexternal[0], IRQ_XIRQ0_LEVEL);
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frv_irq_route(&frv_cpuexternal[1], IRQ_XIRQ1_LEVEL);
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frv_irq_route(&frv_cpuexternal[2], IRQ_XIRQ2_LEVEL);
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frv_irq_route(&frv_cpuexternal[3], IRQ_XIRQ3_LEVEL);
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frv_irq_route(&frv_cpuexternal[4], IRQ_XIRQ4_LEVEL);
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frv_irq_route(&frv_cpuexternal[5], IRQ_XIRQ5_LEVEL);
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frv_irq_route(&frv_cpuexternal[6], IRQ_XIRQ6_LEVEL);
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frv_irq_route(&frv_cpuexternal[7], IRQ_XIRQ7_LEVEL);
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set_IRR(2, IRQ_XIRQ7_LEVEL, IRQ_XIRQ6_LEVEL, IRQ_XIRQ5_LEVEL, IRQ_XIRQ4_LEVEL);
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set_IRR(3, IRQ_XIRQ3_LEVEL, IRQ_XIRQ2_LEVEL, IRQ_XIRQ1_LEVEL, IRQ_XIRQ0_LEVEL);
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#if defined(CONFIG_MB93091_VDK)
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__set_TM1(0x55550000); /* XIRQ7-0 all active low */
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#elif defined(CONFIG_MB93093_PDK)
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__set_TM1(0x15550000); /* XIRQ7 active high, 6-0 all active low */
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#else
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#error dont know external IRQ trigger levels for this setup
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#endif
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} /* end route_cpu_irqs() */
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