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59f0ec231f
Contrary to what the datasheet says, the pre divider doesn't seem to be
incremented by one in the PLL2, but just uses the value from the register,
with 0 being a bypass.
This fixes the audio playing too fast.
Since we now have the same pre-divider flags, and the only difference with
the A10 is the post-divider offset, also remove the structure to just pass
the offset as an argument.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Fixes:
|
||
|---|---|---|
| .. | ||
| clk-a10-codec.c | ||
| clk-a10-hosc.c | ||
| clk-a10-mod1.c | ||
| clk-a10-pll2.c | ||
| clk-a20-gmac.c | ||
| clk-factors.c | ||
| clk-factors.h | ||
| clk-mod0.c | ||
| clk-simple-gates.c | ||
| clk-sun6i-apb0-gates.c | ||
| clk-sun6i-apb0.c | ||
| clk-sun6i-ar100.c | ||
| clk-sun8i-apb0.c | ||
| clk-sun8i-mbus.c | ||
| clk-sun9i-core.c | ||
| clk-sun9i-mmc.c | ||
| clk-sunxi.c | ||
| clk-usb.c | ||
| Makefile | ||