Bruce Allan c6e7f51e73 e1000e: workaround invalid Tx/Rx tail descriptor register write ... When the Manageability Engine (ME) is enabled on 82579, it periodically accesses some MAC CSR registers. There is an arbiter in hardware which prevents simultaneous access of these registers by the host software, i.e. the driver. There is a hardware bug in the aribter that signals a host access of the registers later than it actually happens. A write of the Transmit or Receive Descriptor Tail register could result in an incorrect value if the driver and ME perform simultaneous accesses which could result in an access to an invalid memory address. This would return an Unsupported Request which could hang the hardware. Workaround the issue by checking the FWSM register bit24 which is set by ME before it accesses the MAC CSR registers. Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Tested-by: Jeff Pieper <jeffrey.e.pieper@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>		2011-08-13 02:15:38 -07:00
..
82571.c	e1000e: do not disable receiver on 82574/82583	2011-08-11 15:19:06 -07:00
defines.h
e1000.h	e1000e: workaround invalid Tx/Rx tail descriptor register write	2011-08-13 02:15:38 -07:00
es2lan.c	intel drivers: repair missing flush operations	2011-08-04 04:59:07 -07:00
ethtool.c	e1000e: do not disable receiver on 82574/82583	2011-08-11 15:19:06 -07:00
hw.h	e1000e: access multiple PHY registers on same page at the same time	2011-06-09 20:33:36 -07:00
ich8lan.c	e1000e: workaround invalid Tx/Rx tail descriptor register write	2011-08-13 02:15:38 -07:00
lib.c	e1000e: alternate MAC address update	2011-08-11 15:21:05 -07:00
Makefile
netdev.c	e1000e: workaround invalid Tx/Rx tail descriptor register write	2011-08-13 02:15:38 -07:00
param.c
phy.c	intel drivers: repair missing flush operations	2011-08-04 04:59:07 -07:00