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7274a8c229
Merge routines phy.c and phy.h for RTL8192DE. Signed-off-by: Chaoming_Li <chaoming_li@realsil.com.cn> Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Signed-off-by: John W. Linville <linville@tuxdriver.com>
179 lines
5.8 KiB
C
179 lines
5.8 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2009-2010 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __RTL92D_PHY_H__
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#define __RTL92D_PHY_H__
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#define MAX_PRECMD_CNT 16
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#define MAX_RFDEPENDCMD_CNT 16
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#define MAX_POSTCMD_CNT 16
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#define MAX_DOZE_WAITING_TIMES_9x 64
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#define RT_CANNOT_IO(hw) false
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#define HIGHPOWER_RADIOA_ARRAYLEN 22
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#define IQK_ADDA_REG_NUM 16
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#define MAX_TOLERANCE 5
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#define IQK_DELAY_TIME 1
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#define APK_BB_REG_NUM 5
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#define APK_AFE_REG_NUM 16
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#define APK_CURVE_REG_NUM 4
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#define PATH_NUM 2
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#define LOOP_LIMIT 5
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#define MAX_STALL_TIME 50
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#define ANTENNA_DIVERSITY_VALUE 0x80
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#define MAX_TXPWR_IDX_NMODE_92S 63
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#define RESET_CNT_LIMIT 3
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#define IQK_ADDA_REG_NUM 16
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#define IQK_BB_REG_NUM 10
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#define IQK_BB_REG_NUM_test 6
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#define IQK_MAC_REG_NUM 4
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#define RX_INDEX_MAPPING_NUM 15
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#define IQK_DELAY_TIME 1
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#define CT_OFFSET_MAC_ADDR 0X16
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#define CT_OFFSET_CCK_TX_PWR_IDX 0x5A
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#define CT_OFFSET_HT401S_TX_PWR_IDX 0x60
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#define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF 0x66
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#define CT_OFFSET_HT20_TX_PWR_IDX_DIFF 0x69
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#define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF 0x6C
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#define CT_OFFSET_HT40_MAX_PWR_OFFSET 0x6F
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#define CT_OFFSET_HT20_MAX_PWR_OFFSET 0x72
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#define CT_OFFSET_CHANNEL_PLAH 0x75
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#define CT_OFFSET_THERMAL_METER 0x78
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#define CT_OFFSET_RF_OPTION 0x79
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#define CT_OFFSET_VERSION 0x7E
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#define CT_OFFSET_CUSTOMER_ID 0x7F
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enum swchnlcmd_id {
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CMDID_END,
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CMDID_SET_TXPOWEROWER_LEVEL,
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CMDID_BBREGWRITE10,
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CMDID_WRITEPORT_ULONG,
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CMDID_WRITEPORT_USHORT,
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CMDID_WRITEPORT_UCHAR,
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CMDID_RF_WRITEREG,
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};
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struct swchnlcmd {
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enum swchnlcmd_id cmdid;
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u32 para1;
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u32 para2;
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u32 msdelay;
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};
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enum baseband_config_type {
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BASEBAND_CONFIG_PHY_REG = 0,
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BASEBAND_CONFIG_AGC_TAB = 1,
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};
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enum rf_content {
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radioa_txt = 0,
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radiob_txt = 1,
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radioc_txt = 2,
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radiod_txt = 3
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};
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static inline void rtl92d_acquire_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
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unsigned long *flag)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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if (rtlpriv->rtlhal.interfaceindex == 1)
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spin_lock_irqsave(&rtlpriv->locks.cck_and_rw_pagea_lock, *flag);
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}
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static inline void rtl92d_release_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
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unsigned long *flag)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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if (rtlpriv->rtlhal.interfaceindex == 1)
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spin_unlock_irqrestore(&rtlpriv->locks.cck_and_rw_pagea_lock,
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*flag);
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}
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extern u32 rtl92d_phy_query_bb_reg(struct ieee80211_hw *hw,
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u32 regaddr, u32 bitmask);
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extern void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw,
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u32 regaddr, u32 bitmask, u32 data);
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extern u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw,
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enum radio_path rfpath, u32 regaddr,
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u32 bitmask);
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extern void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw,
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enum radio_path rfpath, u32 regaddr,
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u32 bitmask, u32 data);
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extern bool rtl92d_phy_mac_config(struct ieee80211_hw *hw);
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extern bool rtl92d_phy_bb_config(struct ieee80211_hw *hw);
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extern bool rtl92d_phy_rf_config(struct ieee80211_hw *hw);
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extern bool rtl92c_phy_config_rf_with_feaderfile(struct ieee80211_hw *hw,
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enum radio_path rfpath);
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extern void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
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extern void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
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extern void rtl92d_phy_scan_operation_backup(struct ieee80211_hw *hw,
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u8 operation);
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extern void rtl92d_phy_set_bw_mode(struct ieee80211_hw *hw,
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enum nl80211_channel_type ch_type);
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extern u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw);
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bool rtl92d_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
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enum rf_content content,
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enum radio_path rfpath);
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bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
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extern bool rtl92d_phy_set_rf_power_state(struct ieee80211_hw *hw,
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enum rf_pwrstate rfpwr_state);
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void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw);
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void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw);
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u8 rtl92d_get_chnlgroup_fromarray(u8 chnl);
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void rtl92d_phy_set_poweron(struct ieee80211_hw *hw);
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void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw);
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bool rtl92d_phy_check_poweroff(struct ieee80211_hw *hw);
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void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw);
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void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw);
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void rtl92d_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
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void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw);
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void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw);
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void rtl92d_release_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
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unsigned long *flag);
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void rtl92d_acquire_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
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unsigned long *flag);
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u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl);
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void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel);
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void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw);
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#endif
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