Ben Skeggs 5e5a195ecc drm/nouveau/clock: fix missing pll type/addr when matching default entry ...

This issue is a regression from 70790f4f819875e8f390871fd15bbbf823f28e1b,
and causes us to miss a special-case for C51 (NV4E) chipsets and return
the wrong reference frequency for the VPLLs.

Should fix fdo#56202

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

2012-10-22 14:38:06 +10:00

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drm

drm/nouveau/clock: fix missing pll type/addr when matching default entry

2012-10-22 14:38:06 +10:00

stub

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vga

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Makefile

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