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84659ab585
The commit 9a763bf "get rid of mxc_gpio_init" changed gpio_init
and irq_init sequence. Usually we will call set_irq_chained_handler
in gpio_init functions, this should be called after the irq_init
called, otherwise the chained irq can't get propoer irq_chip and this
irq will remain masked even we called set_irq_chained_handler.
Signed-off-by: Jason Wang <jason77.wang@gmail.com>
Tested-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
87 lines
2.2 KiB
C
87 lines
2.2 KiB
C
/*
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* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*
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* Create static mapping between physical to virtual memory.
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*/
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <asm/mach/map.h>
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#include <mach/hardware.h>
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#include <mach/common.h>
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#include <mach/iomux-v3.h>
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/*
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* Define the MX51 memory map.
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*/
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static struct map_desc mxc_io_desc[] __initdata = {
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{
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.virtual = MX51_IRAM_BASE_ADDR_VIRT,
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.pfn = __phys_to_pfn(MX51_IRAM_BASE_ADDR),
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.length = MX51_IRAM_SIZE,
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.type = MT_DEVICE
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}, {
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.virtual = MX51_DEBUG_BASE_ADDR_VIRT,
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.pfn = __phys_to_pfn(MX51_DEBUG_BASE_ADDR),
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.length = MX51_DEBUG_SIZE,
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.type = MT_DEVICE
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}, {
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.virtual = MX51_AIPS1_BASE_ADDR_VIRT,
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.pfn = __phys_to_pfn(MX51_AIPS1_BASE_ADDR),
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.length = MX51_AIPS1_SIZE,
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.type = MT_DEVICE
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}, {
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.virtual = MX51_SPBA0_BASE_ADDR_VIRT,
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.pfn = __phys_to_pfn(MX51_SPBA0_BASE_ADDR),
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.length = MX51_SPBA0_SIZE,
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.type = MT_DEVICE
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}, {
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.virtual = MX51_AIPS2_BASE_ADDR_VIRT,
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.pfn = __phys_to_pfn(MX51_AIPS2_BASE_ADDR),
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.length = MX51_AIPS2_SIZE,
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.type = MT_DEVICE
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},
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};
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/*
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* This function initializes the memory map. It is called during the
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* system startup to create static physical to virtual memory mappings
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* for the IO modules.
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*/
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void __init mx51_map_io(void)
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{
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mxc_set_cpu_type(MXC_CPU_MX51);
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mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
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mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG_BASE_ADDR));
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iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
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}
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int imx51_register_gpios(void);
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void __init mx51_init_irq(void)
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{
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unsigned long tzic_addr;
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void __iomem *tzic_virt;
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if (mx51_revision() < MX51_CHIP_REV_2_0)
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tzic_addr = MX51_TZIC_BASE_ADDR_TO1;
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else
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tzic_addr = MX51_TZIC_BASE_ADDR;
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tzic_virt = ioremap(tzic_addr, SZ_16K);
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if (!tzic_virt)
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panic("unable to map TZIC interrupt controller\n");
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tzic_init_irq(tzic_virt);
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imx51_register_gpios();
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}
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