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dffa4b2f62
The default notifier doesn't make a lot of sense to call in the correctable errors case. Drop it and emit the mcelog decoding hint only in the uncorrectable errors case and when no notifier is registered. Also, limit issuing the "mcelog --ascii" message in the rare case when we dump unreported CEs before panicking. While at it, remove unused old x86_mce_decode_callback from the header. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com> Signed-off-by: Prarit Bhargava <prarit@redhat.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Nagananda Chumbalkar <Nagananda.Chumbalkar@hp.com> Cc: Russ Anderson <rja@sgi.com> Link: http://lkml.kernel.org/r/20110420102349.GB1361@aftab Signed-off-by: Ingo Molnar <mingo@elte.hu>
243 lines
7.3 KiB
C
243 lines
7.3 KiB
C
#ifndef _ASM_X86_MCE_H
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#define _ASM_X86_MCE_H
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#include <linux/types.h>
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#include <asm/ioctls.h>
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/*
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* Machine Check support for x86
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*/
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#define MCG_BANKCNT_MASK 0xff /* Number of Banks */
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#define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */
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#define MCG_EXT_P (1ULL<<9) /* Extended registers available */
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#define MCG_CMCI_P (1ULL<<10) /* CMCI supported */
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#define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */
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#define MCG_EXT_CNT_SHIFT 16
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#define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
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#define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
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#define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
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#define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
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#define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
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#define MCI_STATUS_VAL (1ULL<<63) /* valid error */
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#define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
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#define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
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#define MCI_STATUS_EN (1ULL<<60) /* error enabled */
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#define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
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#define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
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#define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
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#define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
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#define MCI_STATUS_AR (1ULL<<55) /* Action required */
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/* MISC register defines */
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#define MCM_ADDR_SEGOFF 0 /* segment offset */
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#define MCM_ADDR_LINEAR 1 /* linear address */
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#define MCM_ADDR_PHYS 2 /* physical address */
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#define MCM_ADDR_MEM 3 /* memory address */
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#define MCM_ADDR_GENERIC 7 /* generic */
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/* CTL2 register defines */
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#define MCI_CTL2_CMCI_EN (1ULL << 30)
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#define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL
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#define MCJ_CTX_MASK 3
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#define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
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#define MCJ_CTX_RANDOM 0 /* inject context: random */
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#define MCJ_CTX_PROCESS 1 /* inject context: process */
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#define MCJ_CTX_IRQ 2 /* inject context: IRQ */
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#define MCJ_NMI_BROADCAST 4 /* do NMI broadcasting */
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#define MCJ_EXCEPTION 8 /* raise as exception */
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/* Fields are zero when not available */
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struct mce {
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__u64 status;
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__u64 misc;
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__u64 addr;
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__u64 mcgstatus;
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__u64 ip;
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__u64 tsc; /* cpu time stamp counter */
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__u64 time; /* wall time_t when error was detected */
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__u8 cpuvendor; /* cpu vendor as encoded in system.h */
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__u8 inject_flags; /* software inject flags */
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__u16 pad;
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__u32 cpuid; /* CPUID 1 EAX */
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__u8 cs; /* code segment */
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__u8 bank; /* machine check bank */
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__u8 cpu; /* cpu number; obsolete; use extcpu now */
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__u8 finished; /* entry is valid */
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__u32 extcpu; /* linux cpu number that detected the error */
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__u32 socketid; /* CPU socket ID */
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__u32 apicid; /* CPU initial apic ID */
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__u64 mcgcap; /* MCGCAP MSR: machine check capabilities of CPU */
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};
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/*
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* This structure contains all data related to the MCE log. Also
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* carries a signature to make it easier to find from external
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* debugging tools. Each entry is only valid when its finished flag
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* is set.
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*/
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#define MCE_LOG_LEN 32
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struct mce_log {
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char signature[12]; /* "MACHINECHECK" */
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unsigned len; /* = MCE_LOG_LEN */
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unsigned next;
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unsigned flags;
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unsigned recordlen; /* length of struct mce */
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struct mce entry[MCE_LOG_LEN];
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};
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#define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */
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#define MCE_LOG_SIGNATURE "MACHINECHECK"
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#define MCE_GET_RECORD_LEN _IOR('M', 1, int)
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#define MCE_GET_LOG_LEN _IOR('M', 2, int)
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#define MCE_GETCLEAR_FLAGS _IOR('M', 3, int)
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/* Software defined banks */
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#define MCE_EXTENDED_BANK 128
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#define MCE_THERMAL_BANK MCE_EXTENDED_BANK + 0
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#define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1) /* MCE_AMD */
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#define K8_MCE_THRESHOLD_BANK_0 (MCE_THRESHOLD_BASE + 0 * 9)
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#define K8_MCE_THRESHOLD_BANK_1 (MCE_THRESHOLD_BASE + 1 * 9)
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#define K8_MCE_THRESHOLD_BANK_2 (MCE_THRESHOLD_BASE + 2 * 9)
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#define K8_MCE_THRESHOLD_BANK_3 (MCE_THRESHOLD_BASE + 3 * 9)
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#define K8_MCE_THRESHOLD_BANK_4 (MCE_THRESHOLD_BASE + 4 * 9)
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#define K8_MCE_THRESHOLD_BANK_5 (MCE_THRESHOLD_BASE + 5 * 9)
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#define K8_MCE_THRESHOLD_DRAM_ECC (MCE_THRESHOLD_BANK_4 + 0)
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#ifdef __KERNEL__
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extern struct atomic_notifier_head x86_mce_decoder_chain;
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#include <linux/percpu.h>
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#include <linux/init.h>
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#include <asm/atomic.h>
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extern int mce_disabled;
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extern int mce_p5_enabled;
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#ifdef CONFIG_X86_MCE
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int mcheck_init(void);
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void mcheck_cpu_init(struct cpuinfo_x86 *c);
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#else
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static inline int mcheck_init(void) { return 0; }
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static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
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#endif
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#ifdef CONFIG_X86_ANCIENT_MCE
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void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
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void winchip_mcheck_init(struct cpuinfo_x86 *c);
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static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
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#else
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static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
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static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
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static inline void enable_p5_mce(void) {}
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#endif
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void mce_setup(struct mce *m);
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void mce_log(struct mce *m);
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DECLARE_PER_CPU(struct sys_device, mce_dev);
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/*
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* Maximum banks number.
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* This is the limit of the current register layout on
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* Intel CPUs.
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*/
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#define MAX_NR_BANKS 32
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#ifdef CONFIG_X86_MCE_INTEL
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extern int mce_cmci_disabled;
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extern int mce_ignore_ce;
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void mce_intel_feature_init(struct cpuinfo_x86 *c);
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void cmci_clear(void);
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void cmci_reenable(void);
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void cmci_rediscover(int dying);
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void cmci_recheck(void);
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#else
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static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
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static inline void cmci_clear(void) {}
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static inline void cmci_reenable(void) {}
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static inline void cmci_rediscover(int dying) {}
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static inline void cmci_recheck(void) {}
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#endif
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#ifdef CONFIG_X86_MCE_AMD
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void mce_amd_feature_init(struct cpuinfo_x86 *c);
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#else
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static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
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#endif
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int mce_available(struct cpuinfo_x86 *c);
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DECLARE_PER_CPU(unsigned, mce_exception_count);
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DECLARE_PER_CPU(unsigned, mce_poll_count);
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extern atomic_t mce_entry;
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typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
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DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
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enum mcp_flags {
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MCP_TIMESTAMP = (1 << 0), /* log time stamp */
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MCP_UC = (1 << 1), /* log uncorrected errors */
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MCP_DONTLOG = (1 << 2), /* only clear, don't log */
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};
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void machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
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int mce_notify_irq(void);
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void mce_notify_process(void);
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DECLARE_PER_CPU(struct mce, injectm);
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extern struct file_operations mce_chrdev_ops;
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/*
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* Exception handler
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*/
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/* Call the installed machine check handler for this CPU setup. */
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extern void (*machine_check_vector)(struct pt_regs *, long error_code);
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void do_machine_check(struct pt_regs *, long);
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/*
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* Threshold handler
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*/
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extern void (*mce_threshold_vector)(void);
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extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
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/*
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* Thermal handler
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*/
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void intel_init_thermal(struct cpuinfo_x86 *c);
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void mce_log_therm_throt_event(__u64 status);
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/* Interrupt Handler for core thermal thresholds */
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extern int (*platform_thermal_notify)(__u64 msr_val);
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#ifdef CONFIG_X86_THERMAL_VECTOR
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extern void mcheck_intel_therm_init(void);
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#else
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static inline void mcheck_intel_therm_init(void) { }
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#endif
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/*
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* Used by APEI to report memory error via /dev/mcelog
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*/
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struct cper_sec_mem_err;
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extern void apei_mce_report_mem_error(int corrected,
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struct cper_sec_mem_err *mem_err);
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#endif /* __KERNEL__ */
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#endif /* _ASM_X86_MCE_H */
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