mirror of
https://github.com/FEX-Emu/linux.git
synced 2024-12-29 13:00:35 +00:00
cf0d19fb30
add simple-bus compatible property to soc nodes for 83xx/85xx platforms
that were missing them. Add same to platform probe code.
This fixes SoC device drivers (such as talitos) to succeed in matching
devices present in the soc node.
also update mpc836x_rdk dts to new SEC bindings (overlooked in commit
3fd4473: powerpc/fsl: update crypto node definition and device tree
instances).
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
335 lines
7.9 KiB
Plaintext
335 lines
7.9 KiB
Plaintext
/*
|
|
* MPC832x RDB Device Tree Source
|
|
*
|
|
* Copyright 2007 Freescale Semiconductor Inc.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms of the GNU General Public License as published by the
|
|
* Free Software Foundation; either version 2 of the License, or (at your
|
|
* option) any later version.
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
/ {
|
|
model = "MPC8323ERDB";
|
|
compatible = "MPC8323ERDB", "MPC832xRDB", "MPC83xxRDB";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
aliases {
|
|
ethernet0 = &enet0;
|
|
ethernet1 = &enet1;
|
|
serial0 = &serial0;
|
|
serial1 = &serial1;
|
|
pci0 = &pci0;
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
PowerPC,8323@0 {
|
|
device_type = "cpu";
|
|
reg = <0x0>;
|
|
d-cache-line-size = <0x20>; // 32 bytes
|
|
i-cache-line-size = <0x20>; // 32 bytes
|
|
d-cache-size = <16384>; // L1, 16K
|
|
i-cache-size = <16384>; // L1, 16K
|
|
timebase-frequency = <0>;
|
|
bus-frequency = <0>;
|
|
clock-frequency = <0>;
|
|
};
|
|
};
|
|
|
|
memory {
|
|
device_type = "memory";
|
|
reg = <0x00000000 0x04000000>;
|
|
};
|
|
|
|
soc8323@e0000000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
device_type = "soc";
|
|
compatible = "simple-bus";
|
|
ranges = <0x0 0xe0000000 0x00100000>;
|
|
reg = <0xe0000000 0x00000200>;
|
|
bus-frequency = <0>;
|
|
|
|
wdt@200 {
|
|
device_type = "watchdog";
|
|
compatible = "mpc83xx_wdt";
|
|
reg = <0x200 0x100>;
|
|
};
|
|
|
|
i2c@3000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
cell-index = <0>;
|
|
compatible = "fsl-i2c";
|
|
reg = <0x3000 0x100>;
|
|
interrupts = <14 0x8>;
|
|
interrupt-parent = <&ipic>;
|
|
dfsrr;
|
|
};
|
|
|
|
serial0: serial@4500 {
|
|
cell-index = <0>;
|
|
device_type = "serial";
|
|
compatible = "ns16550";
|
|
reg = <0x4500 0x100>;
|
|
clock-frequency = <0>;
|
|
interrupts = <9 0x8>;
|
|
interrupt-parent = <&ipic>;
|
|
};
|
|
|
|
serial1: serial@4600 {
|
|
cell-index = <1>;
|
|
device_type = "serial";
|
|
compatible = "ns16550";
|
|
reg = <0x4600 0x100>;
|
|
clock-frequency = <0>;
|
|
interrupts = <10 0x8>;
|
|
interrupt-parent = <&ipic>;
|
|
};
|
|
|
|
dma@82a8 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "fsl,mpc8323-dma", "fsl,elo-dma";
|
|
reg = <0x82a8 4>;
|
|
ranges = <0 0x8100 0x1a8>;
|
|
interrupt-parent = <&ipic>;
|
|
interrupts = <71 8>;
|
|
cell-index = <0>;
|
|
dma-channel@0 {
|
|
compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
|
|
reg = <0 0x80>;
|
|
interrupt-parent = <&ipic>;
|
|
interrupts = <71 8>;
|
|
};
|
|
dma-channel@80 {
|
|
compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
|
|
reg = <0x80 0x80>;
|
|
interrupt-parent = <&ipic>;
|
|
interrupts = <71 8>;
|
|
};
|
|
dma-channel@100 {
|
|
compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
|
|
reg = <0x100 0x80>;
|
|
interrupt-parent = <&ipic>;
|
|
interrupts = <71 8>;
|
|
};
|
|
dma-channel@180 {
|
|
compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
|
|
reg = <0x180 0x28>;
|
|
interrupt-parent = <&ipic>;
|
|
interrupts = <71 8>;
|
|
};
|
|
};
|
|
|
|
crypto@30000 {
|
|
compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
|
|
reg = <0x30000 0x10000>;
|
|
interrupts = <11 0x8>;
|
|
interrupt-parent = <&ipic>;
|
|
fsl,num-channels = <1>;
|
|
fsl,channel-fifo-len = <24>;
|
|
fsl,exec-units-mask = <0x4c>;
|
|
fsl,descriptor-types-mask = <0x0122003f>;
|
|
};
|
|
|
|
ipic:pic@700 {
|
|
interrupt-controller;
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x700 0x100>;
|
|
device_type = "ipic";
|
|
};
|
|
|
|
par_io@1400 {
|
|
reg = <0x1400 0x100>;
|
|
device_type = "par_io";
|
|
num-ports = <7>;
|
|
|
|
ucc2pio:ucc_pin@02 {
|
|
pio-map = <
|
|
/* port pin dir open_drain assignment has_irq */
|
|
3 4 3 0 2 0 /* MDIO */
|
|
3 5 1 0 2 0 /* MDC */
|
|
3 21 2 0 1 0 /* RX_CLK (CLK16) */
|
|
3 23 2 0 1 0 /* TX_CLK (CLK3) */
|
|
0 18 1 0 1 0 /* TxD0 */
|
|
0 19 1 0 1 0 /* TxD1 */
|
|
0 20 1 0 1 0 /* TxD2 */
|
|
0 21 1 0 1 0 /* TxD3 */
|
|
0 22 2 0 1 0 /* RxD0 */
|
|
0 23 2 0 1 0 /* RxD1 */
|
|
0 24 2 0 1 0 /* RxD2 */
|
|
0 25 2 0 1 0 /* RxD3 */
|
|
0 26 2 0 1 0 /* RX_ER */
|
|
0 27 1 0 1 0 /* TX_ER */
|
|
0 28 2 0 1 0 /* RX_DV */
|
|
0 29 2 0 1 0 /* COL */
|
|
0 30 1 0 1 0 /* TX_EN */
|
|
0 31 2 0 1 0>; /* CRS */
|
|
};
|
|
ucc3pio:ucc_pin@03 {
|
|
pio-map = <
|
|
/* port pin dir open_drain assignment has_irq */
|
|
0 13 2 0 1 0 /* RX_CLK (CLK9) */
|
|
3 24 2 0 1 0 /* TX_CLK (CLK10) */
|
|
1 0 1 0 1 0 /* TxD0 */
|
|
1 1 1 0 1 0 /* TxD1 */
|
|
1 2 1 0 1 0 /* TxD2 */
|
|
1 3 1 0 1 0 /* TxD3 */
|
|
1 4 2 0 1 0 /* RxD0 */
|
|
1 5 2 0 1 0 /* RxD1 */
|
|
1 6 2 0 1 0 /* RxD2 */
|
|
1 7 2 0 1 0 /* RxD3 */
|
|
1 8 2 0 1 0 /* RX_ER */
|
|
1 9 1 0 1 0 /* TX_ER */
|
|
1 10 2 0 1 0 /* RX_DV */
|
|
1 11 2 0 1 0 /* COL */
|
|
1 12 1 0 1 0 /* TX_EN */
|
|
1 13 2 0 1 0>; /* CRS */
|
|
};
|
|
};
|
|
};
|
|
|
|
qe@e0100000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
device_type = "qe";
|
|
compatible = "fsl,qe";
|
|
ranges = <0x0 0xe0100000 0x00100000>;
|
|
reg = <0xe0100000 0x480>;
|
|
brg-frequency = <0>;
|
|
bus-frequency = <198000000>;
|
|
|
|
muram@10000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "fsl,qe-muram", "fsl,cpm-muram";
|
|
ranges = <0x0 0x00010000 0x00004000>;
|
|
|
|
data-only@0 {
|
|
compatible = "fsl,qe-muram-data",
|
|
"fsl,cpm-muram-data";
|
|
reg = <0x0 0x4000>;
|
|
};
|
|
};
|
|
|
|
spi@4c0 {
|
|
cell-index = <0>;
|
|
compatible = "fsl,spi";
|
|
reg = <0x4c0 0x40>;
|
|
interrupts = <2>;
|
|
interrupt-parent = <&qeic>;
|
|
mode = "cpu-qe";
|
|
};
|
|
|
|
spi@500 {
|
|
cell-index = <1>;
|
|
compatible = "fsl,spi";
|
|
reg = <0x500 0x40>;
|
|
interrupts = <1>;
|
|
interrupt-parent = <&qeic>;
|
|
mode = "cpu";
|
|
};
|
|
|
|
enet0: ucc@3000 {
|
|
device_type = "network";
|
|
compatible = "ucc_geth";
|
|
cell-index = <2>;
|
|
reg = <0x3000 0x200>;
|
|
interrupts = <33>;
|
|
interrupt-parent = <&qeic>;
|
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
|
rx-clock-name = "clk16";
|
|
tx-clock-name = "clk3";
|
|
phy-handle = <&phy00>;
|
|
pio-handle = <&ucc2pio>;
|
|
};
|
|
|
|
enet1: ucc@2200 {
|
|
device_type = "network";
|
|
compatible = "ucc_geth";
|
|
cell-index = <3>;
|
|
reg = <0x2200 0x200>;
|
|
interrupts = <34>;
|
|
interrupt-parent = <&qeic>;
|
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
|
rx-clock-name = "clk9";
|
|
tx-clock-name = "clk10";
|
|
phy-handle = <&phy04>;
|
|
pio-handle = <&ucc3pio>;
|
|
};
|
|
|
|
mdio@3120 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x3120 0x18>;
|
|
compatible = "fsl,ucc-mdio";
|
|
|
|
phy00:ethernet-phy@00 {
|
|
interrupt-parent = <&ipic>;
|
|
interrupts = <0>;
|
|
reg = <0x0>;
|
|
device_type = "ethernet-phy";
|
|
};
|
|
phy04:ethernet-phy@04 {
|
|
interrupt-parent = <&ipic>;
|
|
interrupts = <0>;
|
|
reg = <0x4>;
|
|
device_type = "ethernet-phy";
|
|
};
|
|
};
|
|
|
|
qeic:interrupt-controller@80 {
|
|
interrupt-controller;
|
|
compatible = "fsl,qe-ic";
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
reg = <0x80 0x80>;
|
|
big-endian;
|
|
interrupts = <32 0x8 33 0x8>; //high:32 low:33
|
|
interrupt-parent = <&ipic>;
|
|
};
|
|
};
|
|
|
|
pci0: pci@e0008500 {
|
|
cell-index = <1>;
|
|
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
|
interrupt-map = <
|
|
/* IDSEL 0x10 AD16 (USB) */
|
|
0x8000 0x0 0x0 0x1 &ipic 17 0x8
|
|
|
|
/* IDSEL 0x11 AD17 (Mini1)*/
|
|
0x8800 0x0 0x0 0x1 &ipic 18 0x8
|
|
0x8800 0x0 0x0 0x2 &ipic 19 0x8
|
|
0x8800 0x0 0x0 0x3 &ipic 20 0x8
|
|
0x8800 0x0 0x0 0x4 &ipic 48 0x8
|
|
|
|
/* IDSEL 0x12 AD18 (PCI/Mini2) */
|
|
0x9000 0x0 0x0 0x1 &ipic 19 0x8
|
|
0x9000 0x0 0x0 0x2 &ipic 20 0x8
|
|
0x9000 0x0 0x0 0x3 &ipic 48 0x8
|
|
0x9000 0x0 0x0 0x4 &ipic 17 0x8>;
|
|
|
|
interrupt-parent = <&ipic>;
|
|
interrupts = <66 0x8>;
|
|
bus-range = <0x0 0x0>;
|
|
ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
|
|
0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
|
|
0x01000000 0x0 0xd0000000 0xd0000000 0x0 0x04000000>;
|
|
clock-frequency = <0>;
|
|
#interrupt-cells = <1>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
reg = <0xe0008500 0x100>;
|
|
compatible = "fsl,mpc8349-pci";
|
|
device_type = "pci";
|
|
};
|
|
};
|