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68e4798143
According to the datasheet:
Page0 / Register8: Audio Serial Data interface Control Register A
BIT 7: Bit Clock Directional Control
0: Bit clock is an input (slave mode)
1: Bit clock is an output (master mode)
BIT 6: Word Clock Directional Control
0: Word clock is an input (slave mode)
1: Word clock is an output (master mode)
Current code sets BIT_CLK_MASTER and WORD_CLK_MASTER bits for master mode,
but does not clear these bits for slave mode.
Signed-off-by: Axel Lin <axel.lin@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>