Mengdong Lin a07187c992 ALSA: hda - restore BCLK M/N values when resuming HSW/BDW display controller ... For Intel Haswell/Broadwell display HD-A controller, the 24MHz HD-A link BCLK is converted from Core Display Clock (CDCLK): BCLK = CDCLK * M / N And there are two registers EM4 and EM5 to program M, N value respectively. The EM4/EM5 values will be lost and when the display power well is disabled. BIOS programs CDCLK selected by OEM and EM4/EM5, but BIOS has no idea about display power well on/off at runtime. So the M/N can be wrong if non-default CDCLK is used when the audio controller resumes, which results in an invalid BCLK and abnormal audio playback rate. So this patch saves and restores valid M/N values on controller suspend/resume. And 'struct hda_intel' is defined to contain standard HD-A 'struct azx' and Intel specific fields, as Takashi suggested. Signed-off-by: Mengdong Lin <mengdong.lin@intel.com> Cc: <stable@vger.kernel.org> Signed-off-by: Takashi Iwai <tiwai@suse.de>		2014-06-26 15:47:42 +02:00
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aoa
arm
atmel
core	ALSA: control: Make sure that id->index does not overflow	2014-06-18 15:13:37 +02:00
drivers
firewire
i2c
isa
mips
oss
parisc
pci	ALSA: hda - restore BCLK M/N values when resuming HSW/BDW display controller	2014-06-26 15:47:42 +02:00
pcmcia
ppc
sh
soc	Merge remote-tracking branches 'asoc/fix/fsl-dma', 'asoc/fix/fsl-spdif', 'asoc/fix/pxa', 'asoc/fix/rcar' and 'asoc/fix/sigmadsp' into asoc-linus	2014-06-16 16:05:16 +01:00
sparc
spi
synth
usb	ALSA: usb-audio: Fix races at disconnection and PCM closing	2014-06-26 10:33:35 +02:00
ac97_bus.c
Kconfig
last.c
Makefile
sound_core.c
sound_firmware.c