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6c0cc950ae
The ACPI handles of PCI root bridges need to be known to acpi_bind_one(), so that it can create the appropriate "firmware_node" and "physical_node" files for them, but currently the way it gets to know those handles is not exactly straightforward (to put it lightly). This is how it works, roughly: 1. acpi_bus_scan() finds the handle of a PCI root bridge, creates a struct acpi_device object for it and passes that object to acpi_pci_root_add(). 2. acpi_pci_root_add() creates a struct acpi_pci_root object, populates its "device" field with its argument's address (device->handle is the ACPI handle found in step 1). 3. The struct acpi_pci_root object created in step 2 is passed to pci_acpi_scan_root() and used to get resources that are passed to pci_create_root_bus(). 4. pci_create_root_bus() creates a struct pci_host_bridge object and passes its "dev" member to device_register(). 5. platform_notify(), which for systems with ACPI is set to acpi_platform_notify(), is called. So far, so good. Now it starts to be "interesting". 6. acpi_find_bridge_device() is used to find the ACPI handle of the given device (which is the PCI root bridge) and executes acpi_pci_find_root_bridge(), among other things, for the given device object. 7. acpi_pci_find_root_bridge() uses the name (sic!) of the given device object to extract the segment and bus numbers of the PCI root bridge and passes them to acpi_get_pci_rootbridge_handle(). 8. acpi_get_pci_rootbridge_handle() browses the list of ACPI PCI root bridges and finds the one that matches the given segment and bus numbers. Its handle is then used to initialize the ACPI handle of the PCI root bridge's device object by acpi_bind_one(). However, this is *exactly* the ACPI handle we started with in step 1. Needless to say, this is quite embarassing, but it may be avoided thanks to commit f3fd0c8 (ACPI: Allow ACPI handles of devices to be initialized in advance), which makes it possible to initialize the ACPI handle of a device before passing it to device_register(). Accordingly, add a new __weak routine, pcibios_root_bridge_prepare(), defaulting to an empty implementation that can be replaced by the interested architecutres (x86 and ia64 at the moment) with functions that will set the root bridge's ACPI handle before its dev member is passed to device_register(). Make both x86 and ia64 provide such implementations of pcibios_root_bridge_prepare() and remove acpi_pci_find_root_bridge() and acpi_get_pci_rootbridge_handle() that aren't necessary any more. Included is a fix for breakage on systems with non-ACPI PCI host bridges from Bjorn Helgaas. Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
631 lines
15 KiB
C
631 lines
15 KiB
C
#include <linux/pci.h>
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#include <linux/acpi.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/dmi.h>
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#include <linux/slab.h>
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#include <asm/numa.h>
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#include <asm/pci_x86.h>
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struct pci_root_info {
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struct acpi_device *bridge;
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char name[16];
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unsigned int res_num;
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struct resource *res;
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resource_size_t *res_offset;
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struct pci_sysdata sd;
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#ifdef CONFIG_PCI_MMCONFIG
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bool mcfg_added;
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u16 segment;
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u8 start_bus;
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u8 end_bus;
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#endif
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};
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static bool pci_use_crs = true;
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static bool pci_ignore_seg = false;
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static int __init set_use_crs(const struct dmi_system_id *id)
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{
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pci_use_crs = true;
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return 0;
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}
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static int __init set_nouse_crs(const struct dmi_system_id *id)
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{
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pci_use_crs = false;
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return 0;
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}
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static int __init set_ignore_seg(const struct dmi_system_id *id)
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{
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printk(KERN_INFO "PCI: %s detected: ignoring ACPI _SEG\n", id->ident);
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pci_ignore_seg = true;
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return 0;
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}
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static const struct dmi_system_id pci_crs_quirks[] __initconst = {
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/* http://bugzilla.kernel.org/show_bug.cgi?id=14183 */
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{
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.callback = set_use_crs,
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.ident = "IBM System x3800",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
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DMI_MATCH(DMI_PRODUCT_NAME, "x3800"),
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},
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},
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/* https://bugzilla.kernel.org/show_bug.cgi?id=16007 */
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/* 2006 AMD HT/VIA system with two host bridges */
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{
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.callback = set_use_crs,
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.ident = "ASRock ALiveSATA2-GLAN",
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.matches = {
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DMI_MATCH(DMI_PRODUCT_NAME, "ALiveSATA2-GLAN"),
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},
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},
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/* https://bugzilla.kernel.org/show_bug.cgi?id=30552 */
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/* 2006 AMD HT/VIA system with two host bridges */
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{
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.callback = set_use_crs,
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.ident = "ASUS M2V-MX SE",
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.matches = {
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DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
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DMI_MATCH(DMI_BOARD_NAME, "M2V-MX SE"),
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DMI_MATCH(DMI_BIOS_VENDOR, "American Megatrends Inc."),
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},
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},
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/* https://bugzilla.kernel.org/show_bug.cgi?id=42619 */
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{
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.callback = set_use_crs,
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.ident = "MSI MS-7253",
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.matches = {
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DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
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DMI_MATCH(DMI_BOARD_NAME, "MS-7253"),
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DMI_MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies, LTD"),
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},
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},
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/* Now for the blacklist.. */
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/* https://bugzilla.redhat.com/show_bug.cgi?id=769657 */
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{
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.callback = set_nouse_crs,
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.ident = "Dell Studio 1557",
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.matches = {
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DMI_MATCH(DMI_BOARD_VENDOR, "Dell Inc."),
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DMI_MATCH(DMI_PRODUCT_NAME, "Studio 1557"),
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DMI_MATCH(DMI_BIOS_VERSION, "A09"),
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},
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},
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/* https://bugzilla.redhat.com/show_bug.cgi?id=769657 */
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{
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.callback = set_nouse_crs,
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.ident = "Thinkpad SL510",
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.matches = {
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DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
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DMI_MATCH(DMI_BOARD_NAME, "2847DFG"),
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DMI_MATCH(DMI_BIOS_VERSION, "6JET85WW (1.43 )"),
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},
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},
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/* https://bugzilla.kernel.org/show_bug.cgi?id=15362 */
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{
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.callback = set_ignore_seg,
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.ident = "HP xw9300",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
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DMI_MATCH(DMI_PRODUCT_NAME, "HP xw9300 Workstation"),
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},
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},
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{}
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};
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void __init pci_acpi_crs_quirks(void)
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{
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int year;
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if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) && year < 2008)
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pci_use_crs = false;
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dmi_check_system(pci_crs_quirks);
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/*
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* If the user specifies "pci=use_crs" or "pci=nocrs" explicitly, that
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* takes precedence over anything we figured out above.
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*/
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if (pci_probe & PCI_ROOT_NO_CRS)
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pci_use_crs = false;
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else if (pci_probe & PCI_USE__CRS)
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pci_use_crs = true;
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printk(KERN_INFO "PCI: %s host bridge windows from ACPI; "
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"if necessary, use \"pci=%s\" and report a bug\n",
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pci_use_crs ? "Using" : "Ignoring",
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pci_use_crs ? "nocrs" : "use_crs");
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}
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#ifdef CONFIG_PCI_MMCONFIG
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static int __devinit check_segment(u16 seg, struct device *dev, char *estr)
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{
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if (seg) {
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dev_err(dev,
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"%s can't access PCI configuration "
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"space under this host bridge.\n",
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estr);
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return -EIO;
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}
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/*
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* Failure in adding MMCFG information is not fatal,
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* just can't access extended configuration space of
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* devices under this host bridge.
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*/
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dev_warn(dev,
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"%s can't access extended PCI configuration "
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"space under this bridge.\n",
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estr);
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return 0;
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}
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static int __devinit setup_mcfg_map(struct pci_root_info *info,
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u16 seg, u8 start, u8 end,
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phys_addr_t addr)
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{
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int result;
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struct device *dev = &info->bridge->dev;
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info->start_bus = start;
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info->end_bus = end;
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info->mcfg_added = false;
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/* return success if MMCFG is not in use */
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if (raw_pci_ext_ops && raw_pci_ext_ops != &pci_mmcfg)
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return 0;
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if (!(pci_probe & PCI_PROBE_MMCONF))
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return check_segment(seg, dev, "MMCONFIG is disabled,");
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result = pci_mmconfig_insert(dev, seg, start, end, addr);
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if (result == 0) {
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/* enable MMCFG if it hasn't been enabled yet */
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if (raw_pci_ext_ops == NULL)
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raw_pci_ext_ops = &pci_mmcfg;
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info->mcfg_added = true;
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} else if (result != -EEXIST)
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return check_segment(seg, dev,
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"fail to add MMCONFIG information,");
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return 0;
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}
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static void teardown_mcfg_map(struct pci_root_info *info)
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{
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if (info->mcfg_added) {
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pci_mmconfig_delete(info->segment, info->start_bus,
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info->end_bus);
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info->mcfg_added = false;
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}
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}
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#else
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static int __devinit setup_mcfg_map(struct pci_root_info *info,
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u16 seg, u8 start, u8 end,
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phys_addr_t addr)
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{
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return 0;
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}
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static void teardown_mcfg_map(struct pci_root_info *info)
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{
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}
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#endif
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static acpi_status
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resource_to_addr(struct acpi_resource *resource,
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struct acpi_resource_address64 *addr)
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{
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acpi_status status;
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struct acpi_resource_memory24 *memory24;
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struct acpi_resource_memory32 *memory32;
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struct acpi_resource_fixed_memory32 *fixed_memory32;
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memset(addr, 0, sizeof(*addr));
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switch (resource->type) {
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case ACPI_RESOURCE_TYPE_MEMORY24:
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memory24 = &resource->data.memory24;
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addr->resource_type = ACPI_MEMORY_RANGE;
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addr->minimum = memory24->minimum;
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addr->address_length = memory24->address_length;
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addr->maximum = addr->minimum + addr->address_length - 1;
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return AE_OK;
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case ACPI_RESOURCE_TYPE_MEMORY32:
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memory32 = &resource->data.memory32;
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addr->resource_type = ACPI_MEMORY_RANGE;
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addr->minimum = memory32->minimum;
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addr->address_length = memory32->address_length;
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addr->maximum = addr->minimum + addr->address_length - 1;
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return AE_OK;
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case ACPI_RESOURCE_TYPE_FIXED_MEMORY32:
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fixed_memory32 = &resource->data.fixed_memory32;
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addr->resource_type = ACPI_MEMORY_RANGE;
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addr->minimum = fixed_memory32->address;
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addr->address_length = fixed_memory32->address_length;
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addr->maximum = addr->minimum + addr->address_length - 1;
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return AE_OK;
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case ACPI_RESOURCE_TYPE_ADDRESS16:
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case ACPI_RESOURCE_TYPE_ADDRESS32:
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case ACPI_RESOURCE_TYPE_ADDRESS64:
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status = acpi_resource_to_address64(resource, addr);
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if (ACPI_SUCCESS(status) &&
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(addr->resource_type == ACPI_MEMORY_RANGE ||
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addr->resource_type == ACPI_IO_RANGE) &&
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addr->address_length > 0) {
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return AE_OK;
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}
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break;
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}
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return AE_ERROR;
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}
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static acpi_status
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count_resource(struct acpi_resource *acpi_res, void *data)
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{
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struct pci_root_info *info = data;
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struct acpi_resource_address64 addr;
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acpi_status status;
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status = resource_to_addr(acpi_res, &addr);
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if (ACPI_SUCCESS(status))
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info->res_num++;
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return AE_OK;
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}
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static acpi_status
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setup_resource(struct acpi_resource *acpi_res, void *data)
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{
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struct pci_root_info *info = data;
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struct resource *res;
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struct acpi_resource_address64 addr;
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acpi_status status;
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unsigned long flags;
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u64 start, orig_end, end;
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status = resource_to_addr(acpi_res, &addr);
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if (!ACPI_SUCCESS(status))
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return AE_OK;
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if (addr.resource_type == ACPI_MEMORY_RANGE) {
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flags = IORESOURCE_MEM;
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if (addr.info.mem.caching == ACPI_PREFETCHABLE_MEMORY)
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flags |= IORESOURCE_PREFETCH;
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} else if (addr.resource_type == ACPI_IO_RANGE) {
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flags = IORESOURCE_IO;
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} else
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return AE_OK;
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start = addr.minimum + addr.translation_offset;
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orig_end = end = addr.maximum + addr.translation_offset;
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/* Exclude non-addressable range or non-addressable portion of range */
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end = min(end, (u64)iomem_resource.end);
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if (end <= start) {
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dev_info(&info->bridge->dev,
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"host bridge window [%#llx-%#llx] "
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"(ignored, not CPU addressable)\n", start, orig_end);
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return AE_OK;
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} else if (orig_end != end) {
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dev_info(&info->bridge->dev,
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"host bridge window [%#llx-%#llx] "
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"([%#llx-%#llx] ignored, not CPU addressable)\n",
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start, orig_end, end + 1, orig_end);
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}
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res = &info->res[info->res_num];
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res->name = info->name;
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res->flags = flags;
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res->start = start;
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res->end = end;
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info->res_offset[info->res_num] = addr.translation_offset;
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if (!pci_use_crs) {
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dev_printk(KERN_DEBUG, &info->bridge->dev,
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"host bridge window %pR (ignored)\n", res);
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return AE_OK;
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}
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info->res_num++;
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return AE_OK;
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}
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static void coalesce_windows(struct pci_root_info *info, unsigned long type)
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{
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int i, j;
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struct resource *res1, *res2;
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for (i = 0; i < info->res_num; i++) {
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res1 = &info->res[i];
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if (!(res1->flags & type))
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continue;
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for (j = i + 1; j < info->res_num; j++) {
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res2 = &info->res[j];
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if (!(res2->flags & type))
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continue;
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/*
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* I don't like throwing away windows because then
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* our resources no longer match the ACPI _CRS, but
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* the kernel resource tree doesn't allow overlaps.
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*/
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if (resource_overlaps(res1, res2)) {
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res1->start = min(res1->start, res2->start);
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res1->end = max(res1->end, res2->end);
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dev_info(&info->bridge->dev,
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"host bridge window expanded to %pR; %pR ignored\n",
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res1, res2);
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res2->flags = 0;
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}
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}
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}
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}
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static void add_resources(struct pci_root_info *info,
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struct list_head *resources)
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{
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int i;
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struct resource *res, *root, *conflict;
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coalesce_windows(info, IORESOURCE_MEM);
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coalesce_windows(info, IORESOURCE_IO);
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for (i = 0; i < info->res_num; i++) {
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res = &info->res[i];
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if (res->flags & IORESOURCE_MEM)
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root = &iomem_resource;
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else if (res->flags & IORESOURCE_IO)
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root = &ioport_resource;
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else
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continue;
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conflict = insert_resource_conflict(root, res);
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if (conflict)
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dev_info(&info->bridge->dev,
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"ignoring host bridge window %pR (conflicts with %s %pR)\n",
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res, conflict->name, conflict);
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else
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pci_add_resource_offset(resources, res,
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info->res_offset[i]);
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}
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}
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static void free_pci_root_info_res(struct pci_root_info *info)
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{
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kfree(info->res);
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info->res = NULL;
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kfree(info->res_offset);
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info->res_offset = NULL;
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info->res_num = 0;
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}
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static void __release_pci_root_info(struct pci_root_info *info)
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{
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int i;
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struct resource *res;
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for (i = 0; i < info->res_num; i++) {
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res = &info->res[i];
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if (!res->parent)
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continue;
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if (!(res->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
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continue;
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release_resource(res);
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}
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free_pci_root_info_res(info);
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teardown_mcfg_map(info);
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kfree(info);
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}
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static void release_pci_root_info(struct pci_host_bridge *bridge)
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{
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struct pci_root_info *info = bridge->release_data;
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__release_pci_root_info(info);
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}
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static void
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probe_pci_root_info(struct pci_root_info *info, struct acpi_device *device,
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int busnum, int domain)
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{
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size_t size;
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sprintf(info->name, "PCI Bus %04x:%02x", domain, busnum);
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info->bridge = device;
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info->res_num = 0;
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acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_resource,
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info);
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if (!info->res_num)
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return;
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size = sizeof(*info->res) * info->res_num;
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info->res = kzalloc(size, GFP_KERNEL);
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if (!info->res) {
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info->res_num = 0;
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return;
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}
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size = sizeof(*info->res_offset) * info->res_num;
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info->res_num = 0;
|
|
info->res_offset = kzalloc(size, GFP_KERNEL);
|
|
if (!info->res_offset) {
|
|
kfree(info->res);
|
|
info->res = NULL;
|
|
return;
|
|
}
|
|
|
|
acpi_walk_resources(device->handle, METHOD_NAME__CRS, setup_resource,
|
|
info);
|
|
}
|
|
|
|
struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_pci_root *root)
|
|
{
|
|
struct acpi_device *device = root->device;
|
|
struct pci_root_info *info = NULL;
|
|
int domain = root->segment;
|
|
int busnum = root->secondary.start;
|
|
LIST_HEAD(resources);
|
|
struct pci_bus *bus = NULL;
|
|
struct pci_sysdata *sd;
|
|
int node;
|
|
#ifdef CONFIG_ACPI_NUMA
|
|
int pxm;
|
|
#endif
|
|
|
|
if (pci_ignore_seg)
|
|
domain = 0;
|
|
|
|
if (domain && !pci_domains_supported) {
|
|
printk(KERN_WARNING "pci_bus %04x:%02x: "
|
|
"ignored (multiple domains not supported)\n",
|
|
domain, busnum);
|
|
return NULL;
|
|
}
|
|
|
|
node = -1;
|
|
#ifdef CONFIG_ACPI_NUMA
|
|
pxm = acpi_get_pxm(device->handle);
|
|
if (pxm >= 0)
|
|
node = pxm_to_node(pxm);
|
|
if (node != -1)
|
|
set_mp_bus_to_node(busnum, node);
|
|
else
|
|
#endif
|
|
node = get_mp_bus_to_node(busnum);
|
|
|
|
if (node != -1 && !node_online(node))
|
|
node = -1;
|
|
|
|
info = kzalloc(sizeof(*info), GFP_KERNEL);
|
|
if (!info) {
|
|
printk(KERN_WARNING "pci_bus %04x:%02x: "
|
|
"ignored (out of memory)\n", domain, busnum);
|
|
return NULL;
|
|
}
|
|
|
|
sd = &info->sd;
|
|
sd->domain = domain;
|
|
sd->node = node;
|
|
sd->acpi = device->handle;
|
|
/*
|
|
* Maybe the desired pci bus has been already scanned. In such case
|
|
* it is unnecessary to scan the pci bus with the given domain,busnum.
|
|
*/
|
|
bus = pci_find_bus(domain, busnum);
|
|
if (bus) {
|
|
/*
|
|
* If the desired bus exits, the content of bus->sysdata will
|
|
* be replaced by sd.
|
|
*/
|
|
memcpy(bus->sysdata, sd, sizeof(*sd));
|
|
kfree(info);
|
|
} else {
|
|
probe_pci_root_info(info, device, busnum, domain);
|
|
|
|
/* insert busn res at first */
|
|
pci_add_resource(&resources, &root->secondary);
|
|
/*
|
|
* _CRS with no apertures is normal, so only fall back to
|
|
* defaults or native bridge info if we're ignoring _CRS.
|
|
*/
|
|
if (pci_use_crs)
|
|
add_resources(info, &resources);
|
|
else {
|
|
free_pci_root_info_res(info);
|
|
x86_pci_root_bus_resources(busnum, &resources);
|
|
}
|
|
|
|
if (!setup_mcfg_map(info, domain, (u8)root->secondary.start,
|
|
(u8)root->secondary.end, root->mcfg_addr))
|
|
bus = pci_create_root_bus(NULL, busnum, &pci_root_ops,
|
|
sd, &resources);
|
|
|
|
if (bus) {
|
|
pci_scan_child_bus(bus);
|
|
pci_set_host_bridge_release(
|
|
to_pci_host_bridge(bus->bridge),
|
|
release_pci_root_info, info);
|
|
} else {
|
|
pci_free_resource_list(&resources);
|
|
__release_pci_root_info(info);
|
|
}
|
|
}
|
|
|
|
/* After the PCI-E bus has been walked and all devices discovered,
|
|
* configure any settings of the fabric that might be necessary.
|
|
*/
|
|
if (bus) {
|
|
struct pci_bus *child;
|
|
list_for_each_entry(child, &bus->children, node) {
|
|
struct pci_dev *self = child->self;
|
|
if (!self)
|
|
continue;
|
|
|
|
pcie_bus_configure_settings(child, self->pcie_mpss);
|
|
}
|
|
}
|
|
|
|
if (bus && node != -1) {
|
|
#ifdef CONFIG_ACPI_NUMA
|
|
if (pxm >= 0)
|
|
dev_printk(KERN_DEBUG, &bus->dev,
|
|
"on NUMA node %d (pxm %d)\n", node, pxm);
|
|
#else
|
|
dev_printk(KERN_DEBUG, &bus->dev, "on NUMA node %d\n", node);
|
|
#endif
|
|
}
|
|
|
|
return bus;
|
|
}
|
|
|
|
int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
|
|
{
|
|
struct pci_sysdata *sd = bridge->bus->sysdata;
|
|
|
|
ACPI_HANDLE_SET(&bridge->dev, sd->acpi);
|
|
return 0;
|
|
}
|
|
|
|
int __init pci_acpi_init(void)
|
|
{
|
|
struct pci_dev *dev = NULL;
|
|
|
|
if (acpi_noirq)
|
|
return -ENODEV;
|
|
|
|
printk(KERN_INFO "PCI: Using ACPI for IRQ routing\n");
|
|
acpi_irq_penalty_init();
|
|
pcibios_enable_irq = acpi_pci_irq_enable;
|
|
pcibios_disable_irq = acpi_pci_irq_disable;
|
|
x86_init.pci.init_irq = x86_init_noop;
|
|
|
|
if (pci_routeirq) {
|
|
/*
|
|
* PCI IRQ routing is set up by pci_enable_device(), but we
|
|
* also do it here in case there are still broken drivers that
|
|
* don't use pci_enable_device().
|
|
*/
|
|
printk(KERN_INFO "PCI: Routing PCI interrupts for all devices because \"pci=routeirq\" specified\n");
|
|
for_each_pci_dev(dev)
|
|
acpi_pci_irq_enable(dev);
|
|
}
|
|
|
|
return 0;
|
|
}
|