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Implement the Panasonic MN10300 AM34 CPU subarch and implement SMP support for MN10300. Also implement support for the MN2WS0060 processor and the ASB2364 evaluation board which are AM34 based. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
52 lines
1.6 KiB
C
52 lines
1.6 KiB
C
/* MN10300/AM33v2 Microcontroller SMP registers
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*
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* Copyright (C) 2006 Matsushita Electric Industrial Co., Ltd.
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* All Rights Reserved.
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* Created:
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* 13-Nov-2006 MEI Add extended cache and atomic operation register
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* for SMP support.
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* 23-Feb-2007 MEI Add define for gdbstub SMP.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _ASM_PROC_SMP_REGS_H
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#define _ASM_PROC_SMP_REGS_H
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#ifdef __KERNEL__
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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#endif
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#include <asm/cpu-regs.h>
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/*
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* Reference to the interrupt controllers of other CPUs
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*/
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#define CROSS_ICR_CPU_SHIFT 16
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#define CROSS_GxICR(X, CPU) __SYSREG(0xc4000000 + (X) * 4 + \
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((X) >= 64 && (X) < 192) * 0xf00 + ((CPU) << CROSS_ICR_CPU_SHIFT), u16)
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#define CROSS_GxICR_u8(X, CPU) __SYSREG(0xc4000000 + (X) * 4 + \
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(((X) >= 64) && ((X) < 192)) * 0xf00 + ((CPU) << CROSS_ICR_CPU_SHIFT), u8)
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/* CPU ID register */
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#define CPUID __SYSREGC(0xc0000054, u32)
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#define CPUID_MASK 0x00000007 /* CPU ID mask */
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/* extended cache control register */
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#define ECHCTR __SYSREG(0xc0000c20, u32)
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#define ECHCTR_IBCM 0x00000001 /* instruction cache broad cast mask */
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#define ECHCTR_DBCM 0x00000002 /* data cache broad cast mask */
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#define ECHCTR_ISPM 0x00000004 /* instruction cache snoop mask */
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#define ECHCTR_DSPM 0x00000008 /* data cache snoop mask */
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#define NMIAGR __SYSREG(0xd400013c, u16)
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#define NMIAGR_GN 0x03fc
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#endif /* __KERNEL__ */
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#endif /* _ASM_PROC_SMP_REGS_H */
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