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edd4fc63a3
Re-arrange things a bit so that we can get work requested after a bo fence passes, like pageflip, done before retiring bo's. Without any sort of bo cache in userspace, some games can trigger hundred's of transient bo's, which can cause retire to take a long time (5-10ms). Obviously we want a bo cache.. but this cleanup will make things a bit easier for atomic as well and makes things a bit cleaner. Signed-off-by: Rob Clark <robdclark@gmail.com> Acked-by: David Brown <davidb@codeaurora.org>
249 lines
8.1 KiB
C
249 lines
8.1 KiB
C
/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __MSM_DRV_H__
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#define __MSM_DRV_H__
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/cpufreq.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include <linux/list.h>
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#include <linux/iommu.h>
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#include <linux/types.h>
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#include <asm/sizes.h>
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#ifndef CONFIG_OF
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#include <mach/board.h>
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#include <mach/socinfo.h>
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#include <mach/iommu_domains.h>
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#endif
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#include <drm/drmP.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_fb_helper.h>
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#include <drm/msm_drm.h>
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struct msm_kms;
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struct msm_gpu;
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#define NUM_DOMAINS 2 /* one for KMS, then one per gpu core (?) */
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struct msm_file_private {
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/* currently we don't do anything useful with this.. but when
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* per-context address spaces are supported we'd keep track of
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* the context's page-tables here.
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*/
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int dummy;
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};
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struct msm_drm_private {
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struct msm_kms *kms;
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/* when we have more than one 'msm_gpu' these need to be an array: */
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struct msm_gpu *gpu;
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struct msm_file_private *lastctx;
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struct drm_fb_helper *fbdev;
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uint32_t next_fence, completed_fence;
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wait_queue_head_t fence_event;
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/* list of GEM objects: */
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struct list_head inactive_list;
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struct workqueue_struct *wq;
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/* callbacks deferred until bo is inactive: */
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struct list_head fence_cbs;
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/* registered IOMMU domains: */
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unsigned int num_iommus;
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struct iommu_domain *iommus[NUM_DOMAINS];
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unsigned int num_planes;
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struct drm_plane *planes[8];
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unsigned int num_crtcs;
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struct drm_crtc *crtcs[8];
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unsigned int num_encoders;
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struct drm_encoder *encoders[8];
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unsigned int num_bridges;
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struct drm_bridge *bridges[8];
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unsigned int num_connectors;
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struct drm_connector *connectors[8];
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};
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struct msm_format {
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uint32_t pixel_format;
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};
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/* callback from wq once fence has passed: */
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struct msm_fence_cb {
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struct work_struct work;
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uint32_t fence;
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void (*func)(struct msm_fence_cb *cb);
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};
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void __msm_fence_worker(struct work_struct *work);
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#define INIT_FENCE_CB(_cb, _func) do { \
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INIT_WORK(&(_cb)->work, __msm_fence_worker); \
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(_cb)->func = _func; \
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} while (0)
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/* As there are different display controller blocks depending on the
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* snapdragon version, the kms support is split out and the appropriate
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* implementation is loaded at runtime. The kms module is responsible
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* for constructing the appropriate planes/crtcs/encoders/connectors.
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*/
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struct msm_kms_funcs {
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/* hw initialization: */
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int (*hw_init)(struct msm_kms *kms);
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/* irq handling: */
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void (*irq_preinstall)(struct msm_kms *kms);
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int (*irq_postinstall)(struct msm_kms *kms);
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void (*irq_uninstall)(struct msm_kms *kms);
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irqreturn_t (*irq)(struct msm_kms *kms);
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int (*enable_vblank)(struct msm_kms *kms, struct drm_crtc *crtc);
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void (*disable_vblank)(struct msm_kms *kms, struct drm_crtc *crtc);
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/* misc: */
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const struct msm_format *(*get_format)(struct msm_kms *kms, uint32_t format);
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long (*round_pixclk)(struct msm_kms *kms, unsigned long rate,
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struct drm_encoder *encoder);
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/* cleanup: */
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void (*preclose)(struct msm_kms *kms, struct drm_file *file);
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void (*destroy)(struct msm_kms *kms);
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};
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struct msm_kms {
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const struct msm_kms_funcs *funcs;
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};
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struct msm_kms *mdp4_kms_init(struct drm_device *dev);
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int msm_register_iommu(struct drm_device *dev, struct iommu_domain *iommu);
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int msm_iommu_attach(struct drm_device *dev, struct iommu_domain *iommu,
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const char **names, int cnt);
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int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence,
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struct timespec *timeout);
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void msm_update_fence(struct drm_device *dev, uint32_t fence);
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int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
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struct drm_file *file);
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int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
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int msm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
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uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
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int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id,
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uint32_t *iova);
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int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint32_t *iova);
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struct page **msm_gem_get_pages(struct drm_gem_object *obj);
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void msm_gem_put_pages(struct drm_gem_object *obj);
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void msm_gem_put_iova(struct drm_gem_object *obj, int id);
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int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
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struct drm_mode_create_dumb *args);
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int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
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uint32_t handle, uint64_t *offset);
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struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
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void *msm_gem_prime_vmap(struct drm_gem_object *obj);
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void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
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struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
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size_t size, struct sg_table *sg);
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int msm_gem_prime_pin(struct drm_gem_object *obj);
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void msm_gem_prime_unpin(struct drm_gem_object *obj);
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void *msm_gem_vaddr_locked(struct drm_gem_object *obj);
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void *msm_gem_vaddr(struct drm_gem_object *obj);
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int msm_gem_queue_inactive_cb(struct drm_gem_object *obj,
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struct msm_fence_cb *cb);
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void msm_gem_move_to_active(struct drm_gem_object *obj,
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struct msm_gpu *gpu, bool write, uint32_t fence);
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void msm_gem_move_to_inactive(struct drm_gem_object *obj);
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int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op,
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struct timespec *timeout);
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int msm_gem_cpu_fini(struct drm_gem_object *obj);
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void msm_gem_free_object(struct drm_gem_object *obj);
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int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
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uint32_t size, uint32_t flags, uint32_t *handle);
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struct drm_gem_object *msm_gem_new(struct drm_device *dev,
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uint32_t size, uint32_t flags);
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struct drm_gem_object *msm_gem_import(struct drm_device *dev,
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uint32_t size, struct sg_table *sgt);
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struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
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const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
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struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev,
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struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos);
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struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
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struct drm_file *file, struct drm_mode_fb_cmd2 *mode_cmd);
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struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
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int hdmi_init(struct drm_device *dev, struct drm_encoder *encoder);
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void __init hdmi_register(void);
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void __exit hdmi_unregister(void);
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#ifdef CONFIG_DEBUG_FS
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void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m);
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void msm_gem_describe_objects(struct list_head *list, struct seq_file *m);
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void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
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#endif
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void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
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const char *dbgname);
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void msm_writel(u32 data, void __iomem *addr);
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u32 msm_readl(const void __iomem *addr);
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#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
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#define VERB(fmt, ...) if (0) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
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static inline bool fence_completed(struct drm_device *dev, uint32_t fence)
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{
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struct msm_drm_private *priv = dev->dev_private;
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return priv->completed_fence >= fence;
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}
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static inline int align_pitch(int width, int bpp)
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{
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int bytespp = (bpp + 7) / 8;
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/* adreno needs pitch aligned to 32 pixels: */
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return bytespp * ALIGN(width, 32);
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}
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/* for the generated headers: */
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#define INVALID_IDX(idx) ({BUG(); 0;})
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#define fui(x) ({BUG(); 0;})
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#define util_float_to_half(x) ({BUG(); 0;})
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#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
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/* for conditionally setting boolean flag(s): */
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#define COND(bool, val) ((bool) ? (val) : 0)
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#endif /* __MSM_DRV_H__ */
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