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88b2b32bab
* Convert {ide_hwif_t,ide_pci_device_t}->host_flag to be u16. * Add IDE_HFLAG_POST_SET_MODE host flag to indicate the need to program the host for the transfer mode after programming the device. Set it in au1xxx-ide, amd74xx, cs5530, cs5535, pdc202xx_new, sc1200, pmac and via82cxxx host drivers. * Add IDE_HFLAG_NO_SET_MODE host flag to indicate the need to completely skip programming of host/device for the transfer mode ("smart" hosts). Set it in it821x host driver and check it in ide_tune_dma(). * Add ide_set_pio_mode()/ide_set_dma_mode() helpers and convert all direct ->set_pio_mode/->speedproc users to use these helpers. * Move ide_config_drive_speed() calls from ->set_pio_mode/->speedproc methods to callers. * Rename ->speedproc method to ->set_dma_mode, make it void and update all implementations accordingly. * Update ide_set_xfer_rate() comments. * Unexport ide_config_drive_speed(). v2: * Fix issues noticed by Sergei: - export ide_set_dma_mode() instead of moving ->set_pio_mode abuse wrt to setting DMA modes from sc1200_set_pio_mode() to do_special() - check IDE_HFLAG_NO_SET_MODE in ide_tune_dma() - check for (hwif->set_pio_mode) == NULL in ide_set_pio_mode() - check for (hwif->set_dma_mode) == NULL in ide_set_dma_mode() - return -1 from ide_set_{pio,dma}_mode() if ->set_{pio,dma}_mode == NULL - don't set ->set_{pio,dma}_mode on it821x in "smart" mode - fix build problem in pmac.c - minor fixes in au1xxx-ide.c/cs5530.c/siimage.c - improve patch description Changes in behavior caused by this patch: - HDIO_SET_PIO_MODE ioctl would now return -ENOSYS for attempts to change PIO mode if it821x controller is in "smart" mode - removal of two debugging printk-s (from cs5530.c and sc1200.c) - transfer modes 0x00-0x07 passed from user space may be programmed twice on the device (not really an issue since 0x00 is not supported correctly by any host driver ATM, 0x01 is not supported at all and 0x02-0x07 are invalid) Acked-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
458 lines
11 KiB
C
458 lines
11 KiB
C
/*
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* linux/drivers/ide/pci/sl82c105.c
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*
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* SL82C105/Winbond 553 IDE driver
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*
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* Maintainer unknown.
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*
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* Drive tuning added from Rebel.com's kernel sources
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* -- Russell King (15/11/98) linux@arm.linux.org.uk
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*
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* Merge in Russell's HW workarounds, fix various problems
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* with the timing registers setup.
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* -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org
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*
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* Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
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*/
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/timer.h>
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#include <linux/mm.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/blkdev.h>
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#include <linux/hdreg.h>
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#include <linux/pci.h>
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#include <linux/ide.h>
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#include <asm/io.h>
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#include <asm/dma.h>
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(arg) printk arg
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#else
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#define DBG(fmt,...)
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#endif
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/*
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* SL82C105 PCI config register 0x40 bits.
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*/
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#define CTRL_IDE_IRQB (1 << 30)
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#define CTRL_IDE_IRQA (1 << 28)
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#define CTRL_LEGIRQ (1 << 11)
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#define CTRL_P1F16 (1 << 5)
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#define CTRL_P1EN (1 << 4)
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#define CTRL_P0F16 (1 << 1)
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#define CTRL_P0EN (1 << 0)
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/*
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* Convert a PIO mode and cycle time to the required on/off times
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* for the interface. This has protection against runaway timings.
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*/
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static unsigned int get_pio_timings(ide_drive_t *drive, u8 pio)
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{
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unsigned int cmd_on, cmd_off;
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u8 iordy = 0;
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cmd_on = (ide_pio_timings[pio].active_time + 29) / 30;
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cmd_off = (ide_pio_cycle_time(drive, pio) - 30 * cmd_on + 29) / 30;
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if (cmd_on == 0)
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cmd_on = 1;
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if (cmd_off == 0)
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cmd_off = 1;
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if (pio > 2 || ide_dev_has_iordy(drive->id))
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iordy = 0x40;
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return (cmd_on - 1) << 8 | (cmd_off - 1) | iordy;
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}
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/*
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* Configure the chipset for PIO mode.
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*/
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static void sl82c105_set_pio_mode(ide_drive_t *drive, const u8 pio)
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{
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struct pci_dev *dev = HWIF(drive)->pci_dev;
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int reg = 0x44 + drive->dn * 4;
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u16 drv_ctrl;
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drv_ctrl = get_pio_timings(drive, pio);
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/*
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* Store the PIO timings so that we can restore them
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* in case DMA will be turned off...
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*/
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drive->drive_data &= 0xffff0000;
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drive->drive_data |= drv_ctrl;
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if (!drive->using_dma) {
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/*
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* If we are actually using MW DMA, then we can not
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* reprogram the interface drive control register.
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*/
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pci_write_config_word(dev, reg, drv_ctrl);
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pci_read_config_word (dev, reg, &drv_ctrl);
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}
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printk(KERN_DEBUG "%s: selected %s (%dns) (%04X)\n", drive->name,
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ide_xfer_verbose(pio + XFER_PIO_0),
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ide_pio_cycle_time(drive, pio), drv_ctrl);
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}
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/*
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* Configure the chipset for DMA mode.
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*/
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static void sl82c105_set_dma_mode(ide_drive_t *drive, const u8 speed)
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{
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static u16 mwdma_timings[] = {0x0707, 0x0201, 0x0200};
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u16 drv_ctrl;
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DBG(("sl82c105_tune_chipset(drive:%s, speed:%s)\n",
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drive->name, ide_xfer_verbose(speed)));
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switch (speed) {
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case XFER_MW_DMA_2:
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case XFER_MW_DMA_1:
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case XFER_MW_DMA_0:
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drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0];
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/*
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* Store the DMA timings so that we can actually program
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* them when DMA will be turned on...
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*/
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drive->drive_data &= 0x0000ffff;
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drive->drive_data |= (unsigned long)drv_ctrl << 16;
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/*
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* If we are already using DMA, we just reprogram
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* the drive control register.
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*/
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if (drive->using_dma) {
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struct pci_dev *dev = HWIF(drive)->pci_dev;
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int reg = 0x44 + drive->dn * 4;
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pci_write_config_word(dev, reg, drv_ctrl);
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}
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break;
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default:
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return;
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}
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}
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/*
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* Check to see if the drive and chipset are capable of DMA mode.
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*/
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static int sl82c105_ide_dma_check(ide_drive_t *drive)
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{
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DBG(("sl82c105_ide_dma_check(drive:%s)\n", drive->name));
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if (ide_tune_dma(drive))
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return 0;
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return -1;
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}
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/*
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* The SL82C105 holds off all IDE interrupts while in DMA mode until
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* all DMA activity is completed. Sometimes this causes problems (eg,
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* when the drive wants to report an error condition).
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*
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* 0x7e is a "chip testing" register. Bit 2 resets the DMA controller
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* state machine. We need to kick this to work around various bugs.
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*/
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static inline void sl82c105_reset_host(struct pci_dev *dev)
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{
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u16 val;
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pci_read_config_word(dev, 0x7e, &val);
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pci_write_config_word(dev, 0x7e, val | (1 << 2));
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pci_write_config_word(dev, 0x7e, val & ~(1 << 2));
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}
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/*
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* If we get an IRQ timeout, it might be that the DMA state machine
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* got confused. Fix from Todd Inglett. Details from Winbond.
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*
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* This function is called when the IDE timer expires, the drive
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* indicates that it is READY, and we were waiting for DMA to complete.
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*/
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static void sl82c105_dma_lost_irq(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = hwif->pci_dev;
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u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA;
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u8 dma_cmd;
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printk("sl82c105: lost IRQ, resetting host\n");
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/*
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* Check the raw interrupt from the drive.
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*/
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pci_read_config_dword(dev, 0x40, &val);
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if (val & mask)
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printk("sl82c105: drive was requesting IRQ, but host lost it\n");
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/*
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* Was DMA enabled? If so, disable it - we're resetting the
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* host. The IDE layer will be handling the drive for us.
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*/
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dma_cmd = inb(hwif->dma_command);
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if (dma_cmd & 1) {
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outb(dma_cmd & ~1, hwif->dma_command);
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printk("sl82c105: DMA was enabled\n");
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}
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sl82c105_reset_host(dev);
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}
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/*
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* ATAPI devices can cause the SL82C105 DMA state machine to go gaga.
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* Winbond recommend that the DMA state machine is reset prior to
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* setting the bus master DMA enable bit.
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*
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* The generic IDE core will have disabled the BMEN bit before this
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* function is called.
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*/
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static void sl82c105_dma_start(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = hwif->pci_dev;
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sl82c105_reset_host(dev);
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ide_dma_start(drive);
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}
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static void sl82c105_dma_timeout(ide_drive_t *drive)
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{
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DBG(("sl82c105_dma_timeout(drive:%s)\n", drive->name));
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sl82c105_reset_host(HWIF(drive)->pci_dev);
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ide_dma_timeout(drive);
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}
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static int sl82c105_ide_dma_on(ide_drive_t *drive)
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{
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struct pci_dev *dev = HWIF(drive)->pci_dev;
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int rc, reg = 0x44 + drive->dn * 4;
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DBG(("sl82c105_ide_dma_on(drive:%s)\n", drive->name));
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rc = __ide_dma_on(drive);
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if (rc == 0) {
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pci_write_config_word(dev, reg, drive->drive_data >> 16);
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printk(KERN_INFO "%s: DMA enabled\n", drive->name);
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}
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return rc;
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}
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static void sl82c105_dma_off_quietly(ide_drive_t *drive)
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{
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struct pci_dev *dev = HWIF(drive)->pci_dev;
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int reg = 0x44 + drive->dn * 4;
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DBG(("sl82c105_dma_off_quietly(drive:%s)\n", drive->name));
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pci_write_config_word(dev, reg, drive->drive_data);
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ide_dma_off_quietly(drive);
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}
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/*
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* Ok, that is nasty, but we must make sure the DMA timings
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* won't be used for a PIO access. The solution here is
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* to make sure the 16 bits mode is diabled on the channel
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* when DMA is enabled, thus causing the chip to use PIO0
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* timings for those operations.
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*/
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static void sl82c105_selectproc(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = hwif->pci_dev;
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u32 val, old, mask;
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//DBG(("sl82c105_selectproc(drive:%s)\n", drive->name));
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mask = hwif->channel ? CTRL_P1F16 : CTRL_P0F16;
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old = val = (u32)pci_get_drvdata(dev);
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if (drive->using_dma)
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val &= ~mask;
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else
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val |= mask;
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if (old != val) {
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pci_write_config_dword(dev, 0x40, val);
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pci_set_drvdata(dev, (void *)val);
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}
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}
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/*
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* ATA reset will clear the 16 bits mode in the control
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* register, we need to update our cache
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*/
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static void sl82c105_resetproc(ide_drive_t *drive)
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{
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struct pci_dev *dev = HWIF(drive)->pci_dev;
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u32 val;
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DBG(("sl82c105_resetproc(drive:%s)\n", drive->name));
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pci_read_config_dword(dev, 0x40, &val);
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pci_set_drvdata(dev, (void *)val);
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}
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/*
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* Return the revision of the Winbond bridge
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* which this function is part of.
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*/
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static unsigned int sl82c105_bridge_revision(struct pci_dev *dev)
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{
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struct pci_dev *bridge;
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/*
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* The bridge should be part of the same device, but function 0.
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*/
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bridge = pci_get_bus_and_slot(dev->bus->number,
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PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
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if (!bridge)
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return -1;
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/*
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* Make sure it is a Winbond 553 and is an ISA bridge.
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*/
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if (bridge->vendor != PCI_VENDOR_ID_WINBOND ||
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bridge->device != PCI_DEVICE_ID_WINBOND_83C553 ||
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bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) {
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pci_dev_put(bridge);
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return -1;
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}
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/*
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* We need to find function 0's revision, not function 1
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*/
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pci_dev_put(bridge);
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return bridge->revision;
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}
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/*
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* Enable the PCI device
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*
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* --BenH: It's arch fixup code that should enable channels that
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* have not been enabled by firmware. I decided we can still enable
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* channel 0 here at least, but channel 1 has to be enabled by
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* firmware or arch code. We still set both to 16 bits mode.
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*/
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static unsigned int __devinit init_chipset_sl82c105(struct pci_dev *dev, const char *msg)
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{
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u32 val;
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DBG(("init_chipset_sl82c105()\n"));
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pci_read_config_dword(dev, 0x40, &val);
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val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
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pci_write_config_dword(dev, 0x40, val);
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pci_set_drvdata(dev, (void *)val);
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return dev->irq;
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}
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/*
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* Initialise IDE channel
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*/
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static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif)
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{
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unsigned int rev;
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DBG(("init_hwif_sl82c105(hwif: ide%d)\n", hwif->index));
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hwif->set_pio_mode = &sl82c105_set_pio_mode;
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hwif->set_dma_mode = &sl82c105_set_dma_mode;
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hwif->selectproc = &sl82c105_selectproc;
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hwif->resetproc = &sl82c105_resetproc;
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/*
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* We support 32-bit I/O on this interface, and
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* it doesn't have problems with interrupts.
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*/
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hwif->drives[0].io_32bit = hwif->drives[1].io_32bit = 1;
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hwif->drives[0].unmask = hwif->drives[1].unmask = 1;
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/*
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* We always autotune PIO, this is done before DMA is checked,
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* so there's no risk of accidentally disabling DMA
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*/
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hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
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if (!hwif->dma_base)
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return;
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rev = sl82c105_bridge_revision(hwif->pci_dev);
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if (rev <= 5) {
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/*
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* Never ever EVER under any circumstances enable
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* DMA when the bridge is this old.
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*/
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printk(" %s: Winbond W83C553 bridge revision %d, "
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"BM-DMA disabled\n", hwif->name, rev);
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return;
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}
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hwif->atapi_dma = 1;
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hwif->mwdma_mask = 0x07;
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hwif->ide_dma_check = &sl82c105_ide_dma_check;
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hwif->ide_dma_on = &sl82c105_ide_dma_on;
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hwif->dma_off_quietly = &sl82c105_dma_off_quietly;
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hwif->dma_lost_irq = &sl82c105_dma_lost_irq;
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hwif->dma_start = &sl82c105_dma_start;
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hwif->dma_timeout = &sl82c105_dma_timeout;
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if (!noautodma)
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hwif->autodma = 1;
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hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
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if (hwif->mate)
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hwif->serialized = hwif->mate->serialized = 1;
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}
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static ide_pci_device_t sl82c105_chipset __devinitdata = {
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.name = "W82C105",
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.init_chipset = init_chipset_sl82c105,
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.init_hwif = init_hwif_sl82c105,
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.autodma = NOAUTODMA,
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.enablebits = {{0x40,0x01,0x01}, {0x40,0x10,0x10}},
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.bootable = ON_BOARD,
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.pio_mask = ATA_PIO5,
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};
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static int __devinit sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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return ide_setup_pci_device(dev, &sl82c105_chipset);
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}
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static struct pci_device_id sl82c105_pci_tbl[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105), 0},
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{ 0, },
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};
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MODULE_DEVICE_TABLE(pci, sl82c105_pci_tbl);
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static struct pci_driver driver = {
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.name = "W82C105_IDE",
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.id_table = sl82c105_pci_tbl,
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.probe = sl82c105_init_one,
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};
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static int __init sl82c105_ide_init(void)
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{
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return ide_pci_register_driver(&driver);
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}
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module_init(sl82c105_ide_init);
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MODULE_DESCRIPTION("PCI driver module for W82C105 IDE");
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MODULE_LICENSE("GPL");
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