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1bb8866677
Handling timing parameters in a driver's own way should be avoided
because it duplicates efforts of drivers/mtd/nand/nand_timings.c
Besides, this driver hard-codes Intel specific parameters such as
CLK_X=5, CLK_MULTI=4. Taking a certain device (Samsung K9WAG08U1A)
into account by get_samsung_nand_para() is weird as well.
Now, the core framework provides .setup_data_interface() hook, which
handles timing parameters in a generic manner.
While I am working on this, I found even more issues in the current
code, so fixed the following as well:
- In recent IP versions, WE_2_RE and TWHR2 share the same register.
Likewise for ADDR_2_DATA and TCWAW, CS_SETUP_CNT and TWB. When
updating one, the other must be masked. Otherwise, the other will
be set to 0, then timing settings will be broken.
- The recent IP release expanded the ADDR_2_DATA to 7-bit wide.
This register is related to tADL. As commit 74a332e78e ("mtd:
nand: timings: Fix tADL_min for ONFI 4.0 chips") addressed, the
ONFi 4.0 increased the minimum of tADL to 400 nsec. This may not
fit in the 6-bit ADDR_2_DATA in older versions. Check the IP
revision and handle this correctly, otherwise the register value
would wrap around.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
127 lines
3.3 KiB
C
127 lines
3.3 KiB
C
/*
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* NAND Flash Controller Device Driver
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* Copyright © 2009-2010, Intel Corporation and its suppliers.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include "denali.h"
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#define DENALI_NAND_NAME "denali-nand-pci"
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#define INTEL_CE4100 1
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#define INTEL_MRST 2
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/* List of platforms this NAND controller has be integrated into */
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static const struct pci_device_id denali_pci_ids[] = {
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{ PCI_VDEVICE(INTEL, 0x0701), INTEL_CE4100 },
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{ PCI_VDEVICE(INTEL, 0x0809), INTEL_MRST },
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{ /* end: all zeroes */ }
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};
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MODULE_DEVICE_TABLE(pci, denali_pci_ids);
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NAND_ECC_CAPS_SINGLE(denali_pci_ecc_caps, denali_calc_ecc_bytes, 512, 8, 15);
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static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
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{
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int ret;
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resource_size_t csr_base, mem_base;
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unsigned long csr_len, mem_len;
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struct denali_nand_info *denali;
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denali = devm_kzalloc(&dev->dev, sizeof(*denali), GFP_KERNEL);
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if (!denali)
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return -ENOMEM;
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ret = pcim_enable_device(dev);
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if (ret) {
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dev_err(&dev->dev, "Spectra: pci_enable_device failed.\n");
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return ret;
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}
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if (id->driver_data == INTEL_CE4100) {
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mem_base = pci_resource_start(dev, 0);
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mem_len = pci_resource_len(dev, 1);
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csr_base = pci_resource_start(dev, 1);
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csr_len = pci_resource_len(dev, 1);
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} else {
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csr_base = pci_resource_start(dev, 0);
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csr_len = pci_resource_len(dev, 0);
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mem_base = pci_resource_start(dev, 1);
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mem_len = pci_resource_len(dev, 1);
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if (!mem_len) {
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mem_base = csr_base + csr_len;
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mem_len = csr_len;
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}
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}
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pci_set_master(dev);
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denali->dev = &dev->dev;
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denali->irq = dev->irq;
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denali->ecc_caps = &denali_pci_ecc_caps;
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denali->nand.ecc.options |= NAND_ECC_MAXIMIZE;
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denali->clk_x_rate = 200000000; /* 200 MHz */
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ret = pci_request_regions(dev, DENALI_NAND_NAME);
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if (ret) {
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dev_err(&dev->dev, "Spectra: Unable to request memory regions\n");
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return ret;
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}
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denali->flash_reg = ioremap_nocache(csr_base, csr_len);
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if (!denali->flash_reg) {
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dev_err(&dev->dev, "Spectra: Unable to remap memory region\n");
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return -ENOMEM;
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}
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denali->flash_mem = ioremap_nocache(mem_base, mem_len);
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if (!denali->flash_mem) {
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dev_err(&dev->dev, "Spectra: ioremap_nocache failed!");
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ret = -ENOMEM;
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goto failed_remap_reg;
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}
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ret = denali_init(denali);
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if (ret)
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goto failed_remap_mem;
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pci_set_drvdata(dev, denali);
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return 0;
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failed_remap_mem:
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iounmap(denali->flash_mem);
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failed_remap_reg:
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iounmap(denali->flash_reg);
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return ret;
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}
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/* driver exit point */
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static void denali_pci_remove(struct pci_dev *dev)
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{
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struct denali_nand_info *denali = pci_get_drvdata(dev);
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denali_remove(denali);
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iounmap(denali->flash_reg);
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iounmap(denali->flash_mem);
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}
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static struct pci_driver denali_pci_driver = {
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.name = DENALI_NAND_NAME,
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.id_table = denali_pci_ids,
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.probe = denali_pci_probe,
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.remove = denali_pci_remove,
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};
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module_pci_driver(denali_pci_driver);
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