Tejun Heo 3a9e3a51dd jmicron: update quirk for JMB361/3/5/6 ... Set bits 0, 4, 5 and 7 of PCI configuration register 0x40 in the quirk. This has the following effects and is recommended by the vendor. * Force enable of IDE channels (used to be left alone as BIOS configured) * Change initial phase behavior of PIO cycle such that the host pulls down the bus instead of tristating it. Vendor recommends this setting. The above settings are better for the current generation of controllers and needed for the upcoming next generation. Tested on JMB363. Signed-off-by: Tejun Heo <htejun@gmail.com> Cc: Ethan Hsiao <ethanhsiao@jmicron.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>		2007-10-23 21:20:02 -04:00
..
hotplug
pcie
.gitignore
access.c
bus.c
dmar.c
hotplug.c
htirq.c
intel-iommu.c	intel-iommu: fix sg_page()	2007-10-23 09:49:33 +02:00
intel-iommu.h	Intel IOMMU: Iommu Gfx workaround	2007-10-22 08:13:19 -07:00
iova.c	intel-iommu: optimize sg map/unmap calls	2007-10-22 08:13:19 -07:00
iova.h	intel-iommu: optimize sg map/unmap calls	2007-10-22 08:13:19 -07:00
Kconfig
Makefile	Intel IOMMU: Intel IOMMU driver	2007-10-22 08:13:18 -07:00
msi.c
msi.h
pci-acpi.c
pci-driver.c
pci-sysfs.c
pci.c
pci.h	Intel IOMMU: PCI generic helper function	2007-10-22 08:13:18 -07:00
probe.c	Intel IOMMU: PCI generic helper function	2007-10-22 08:13:18 -07:00
proc.c
quirks.c	jmicron: update quirk for JMB361/3/5/6	2007-10-23 21:20:02 -04:00
remove.c
rom.c
search.c	Intel IOMMU: PCI generic helper function	2007-10-22 08:13:18 -07:00
setup-bus.c
setup-irq.c
setup-res.c
syscall.c